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參數(shù)資料
| 型號： | AD9992BBCZ |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 消費家電 |
| 英文描述： | 12-Bit CCD Signal Processor with Precision Timing Generator |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PBGA105 |
| 封裝： | 8 X 8 MM, 0.65 MM PITCH, ROHS COMPLIANT, MO-225, CSPBGA-105 |
| 文件頁數(shù)： | 62/92頁 |
| 文件大小： | 718K |
| 代理商： | AD9992BBCZ |
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AD9992
ANALOG FRONT-END DESCRIPTION AND OPERATION
Rev. 0 | Page 62 of 92
6dB ~ 42dB
CCDIN
CLI
DIGITAL
FILTER
CLPOB
DC RESTORE
OPTICAL BLACK
CLAMP
12-BIT
ADC
VGA
DAC
CDS
INTERNAL
V
REF
2V FULL SCALE
PRECISION
TIMING
GENERATION
SHPSHD
1.2V
OUTPUT
DATA
LATCH
REFT
REFB
V-H
TIMING
GENERATION
SHP SHD
DOUTPHASE
CLPOB
PBLK
0.4V
1.4V
AD9992
0.1μF
VGA GAIN
REGISTER
0.1μF
0.1μF
CLAMP LEVEL
REGISTER
12
PBLK
–3dB, 0dB,
+3dB, +6dB
PBLK
PBLK (WHEN DCBYP = 1)
SHP
S1
1
S2
1
BLANK TO
ZERO OR
CLAMP LEVEL
1
S1 IS NORMALLY CLOSED; S2 IS NORMALLY OPEN.
CDS GAIN
REGISTER
VD
HD
DOUT
DOUTPHASE
DCLK
DCLK
MODE
FIXED
DELAY
CLI
1
0
DCLKINV
0
Figure 71. Analog Front-End Functional Block Diagram
The AD9992 signal processing chain is shown in Figure 71.
Each processing step is essential for achieving a high quality
image from the raw CCD pixel data.
DC Restore
To reduce the large dc offset of the CCD output signal, a dc
restore circuit is used with an external 0.1 μF series coupling
capacitor. This restores the dc level of the CCD signal to
approximately 1.2 V, making it compatible with the 1.8 V core
supply voltage of the AD9992. The dc restore switch is active
during the SHP sample pulse time.
The dc restore circuit can be disabled when the optional PBLK
signal is used to isolate large-signal swings from the CCD input
(see Analog Preblanking). Bit [6] of AFE Register Address 0x00
controls whether the dc restore is active during the PBLK interval.
Analog Preblanking
During certain CCD blanking or substrate clocking intervals,
the CCD input signal to the AD9992 can increase in amplitude
beyond the recommended input range. The PBLK signal can be
used to isolate the CDS input from large-signal swings. While
PBLK is active (low), the CDS input is internally shorted to ground.
Note that because the CDS input is shorted during PBLK, the
CLPOB pulse should not be used during the same active time as
the PBLK pulse.
Correlated Double Sampler (CDS)
The CDS circuit samples each CCD pixel twice to extract the
video information and to reject low frequency noise. The
timing shown in Figure 18 illustrates how the two internally
generated CDS clocks, SHP and SHD, are used to sample the
reference level and data level of the CCD signal, respectively. The
placement of the SHP and SHD sampling edges is determined by
the setting of the SHPLOC and SHDLOC registers located at
Address 0x37. Placement of these two clock signals is critical for
achieving the best performance from the CCD.
The CDS gain is variable in three steps by using the AFE
Address 0x04: 3 dB, 0 dB (default), and +3 dB. Improved noise
performance results from using the +3 dB setting, but the input
range will be reduced (see Analog Specifications).
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