參數(shù)資料
型號: AD9992
廠商: Analog Devices, Inc.
英文描述: 12-Bit CCD Signal Processor with Precision Timing Generator
中文描述: 12位CCD信號處理器與精密時序發(fā)生器
文件頁數(shù): 37/92頁
文件大?。?/td> 718K
代理商: AD9992
AD9992
Hold Area Using FREEZE/RESUME Registers
The FREEZE/RESUME registers can also be used to create a
hold area in which the V-outputs are temporarily held and later
continued, starting at the point where they were held. As shown
in Figure 44, this is different than the VMASK_EN register
because the V-outputs continue from where they stopped rather
than continuing from where they would have been. The hold
area temporarily stops the pixel counter for the V-outputs, while
the V-masking allows the counter to continue in the masking
area.
Rev. 0 | Page 37 of 92
V1
V8
HD
NOTES
1. WHEN HOLD = 1 FOR ANY V-SEQUENCE GROUP, THE FREEZE AND RESUME REGISTERS ARE USED TO SPECIFY THE HOLD AREA.
2. ABOVE EXAMPLE: V1 TO V10 ARE ASSIGNED TO GROUP A. HOLD BIT FOR GROUP A = 1.
3. H-COUNTER FOR GROUP A (V1 TO V10) STOPS DURING HOLD AREA.
Figure 44. Hold Area for Group A
V9
HOLD AREA
FOR GROUP A
V10
FREEZE
RESUME
0
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AD9992BBCZ 12-Bit CCD Signal Processor with Precision Timing Generator
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