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參數(shù)資料
| 型號： | AD9985KSTZ-110 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 其它接口 |
| 英文描述： | 110 MSPS/140 MSPS Analog Interface for Flat Panel Displays |
| 中文描述： | SPECIALTY INTERFACE CIRCUIT, PQFP80 |
| 封裝： | LEAD FREE, MS-026BEC, LQFP-80 |
| 文件頁數(shù)： | 17/32頁 |
| 文件大?。?/td> | 349K |
| 代理商： | AD9985KSTZ-110 |
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AD9985
Rev. 0 | Page 17 of 32
Hex
Address
03H
Write and
Read or
Read Only
R/W
Bits
7:3
Default
Value
01******
Register Name
Function
Bits [7:6] VCO Range. Selects VCO frequency range. (See PLL
description.)
Bits [5:3] Charge Pump Current. Varies the current that drives the
low-pass filter. (See PLL description.)
ADC Clock Phase Adjustment. Larger values mean more delay.
(1 LSB = T/32)
Places the clamp signal an integer number of clock periods after the
trailing edge of the Hsync signal.
Number of clock periods that the clamp signal is actively clamping.
Sets the number of pixel clocks that HSOUT will remain active.
**001***
04H
R/W
7:3
10000***
Phase Adjust
05H
R/W
7:0
10000000
Clamp
Placement
Clamp Duration
Hsync Output
Pulsewidth
Red Gain
Green Gain
Blue Gain
Red Offset
Green Offset
Blue Offset
Sync Control
06H
07H
08H
09H
0AH
0BH
0CH
0DH
0EH
R/W
R/W
7:0
7:0
10000000
00100000
R/W
R/W
R/W
R/W
R/W
R/W
R/W
7:0
7:0
7:0
7:1
7:1
7:1
7:0
10000000
10000000
10000000
1000000*
1000000*
1000000*
0*******
Controls ADC input range (contrast) of each respective channel.
Greater values give less contrast.
Controls dc offset (brightness) of each respective channel. Greater
values decrease brightness.
Bit 7 – Hsync Polarity Override. (Logic 0 = Polarity determined by chip,
Logic 1 = Polarity set by Bit 6 in Register 0EH.)
Bit 6 – Hsync Input Polarity. Indicates polarity of incoming Hsync signal
to the PLL. (Logic 0 = Active Low, Logic 1 = Active High.)
Bit 5 – Hsync Output Polarity. (Logic 0 = Logic High Sync, Logic 1 =
Logic Low Sync.)
Bit 4 – Active Hsync Override. If set to Logic 1, the user can select the
Hsync to be used via Bit 3. If set to Logic 0, the active interface is
selected via Bit 6 in Register 14H.
Bit 3 – Active Hsync Select. Logic 0 selects Hsync as the active sync.
Logic 1 selects Sync-on-Green as the active sync. Note that the
indicated Hsync will be used only if Bit 4 is set to Logic 1 or if both
syncs are active. (Bits 1, 7 = Logic 1 in Register 14H.)
Bit 2 – Vsync Output Invert. (Logic 1 = No Invert, Logic 0 = Invert.)
Bit 1 – Active Vsync Override. If set to Logic 1, the user can select the
Vsync to be used via Bit 0. If set to Logic 0, the active interface is
selected via Bit 3 in Register 14H.
Bit 0 – Active Vsync Select. Logic 0 selects raw Vsync as the output
Vsync. Logic 1 selects sync separated Vsync as the output Vsync. Note
that the indicated Vsync will be used only if Bit 1 is set to Logic 1.
Bit 7 – Clamp Function. Chooses between Hsync for Clamp signal or
another external signal to be used for clamping. (Logic 0 = Hsync,
Logic 1 = Clamp.)
Bit 6 – Clamp Polarity. Valid only with external Clamp signal. (Logic 0 =
Active High, Logic 1 Selects Active Low.)
Bit 5 – Coast Select. Logic 0 selects the coast input pins to be used for
the PLL coast. Logic 1 selects Vsync to be used for the PLL coast.
Bit 4 – Coast Polarity Override. (Logic 0 = Polarity determined by chip,
Logic 1 = Polarity set by Bit 3 in Register 0FH.)
Bit 3 – Coast Polarity. Selects polarity of external Coast signal. (Logic 0
= Active Low, Logic 1 = Active High.)
Bit 2 – Seek Mode Override. (Logic 1 = Allow Low Power Mode, Logic 0
= Disallow Low Power Mode.)
Bit 1 – PWRDN. Full Chip Power-Down, Active Low. (Logic 0 = Full Chip
Power-Down, Logic 1 = Normal.)
Sync-on-Green Threshold. Sets the voltage level of the Sync-on-Green
slicer’s comparator.
*1******
**0*****
***0****
****0***
*****0**
******0*
*******0
0FH
R/W
7:1
0*******
*1******
**0*****
***0****
****1***
*****1**
******1*
10H
R/W
7:3
10111***
Sync-on-Green
Threshold
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