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參數(shù)資料
| 型號： | AD9985AKSTZ-110 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 其它接口 |
| 英文描述： | 110 MSPS/140 MSPS Analog Interface for Flat Panel Displays |
| 中文描述： | SPECIALTY INTERFACE CIRCUIT, PQFP80 |
| 封裝： | LEAD FREE, MS-026-BEC, PLASTIC, LQFP-80 |
| 文件頁數(shù)： | 19/32頁 |
| 文件大小： | 344K |
| 代理商： | AD9985AKSTZ-110 |
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AD9985A
Rev. 0 | Page 19 of 32
Hexadecimal
Address
0x16
Write and
Read or
Read-Only
R/W
Bits
7
Default
Value
0*******
Register
Name
Extra PLL
Divider
SOGIN
Bandwidth
Control
Analog Input
Bandwidth
Control
Reserved
Test Register
Test Register
Red Target
Code
Green Target
Code
Blue Target
Code
Reserved
Auto Offset
Enable
Hold Auto
Offset
Reserved
Update Mode
Test Register
Function
Bit 7—Extra PLL Divider. (Logic 0 = off, Logic 1 = extra divide-by-2).
6:5
*00*****
Bits [6:5]—SOGIN Bandwidth Control; 00 = 300 MHz;
01 or 10 = 13 MHz; 11 = 6.5 MHz.
4
***0****
Bit 4—Sets the bandwdith of the red, green and blue analog inputs.
(Logic 0 = 300 MHz, Logic 1 = 7 MHz).
0x17
0x18
0x19
RO
RO
R/W
3:0
7:0
7:0
7:0
****0000
00000100
Reserved.
Reserved.
Reserved.
Target Code for Auto-Offset Operation.
0x1A
R/W
7:0
00000100
Target Code for Auto-Offset Operation.
0x1B
R/W
7:0
00000100
Target Code for Auto-Offset Operation.
0x1C
0x1D
R/W
R/W
7:0
7
00010001
0*******
Must be written to 0x11 for proper operation.
Enables the auto-offset circuitry.
6
*0******
Holds the offset output of the auto-offset at the current value.
0x1E
R/W
5:2
1:0
7:0
**1001**
******10
0000****
Must be written to 9 for proper operation.
Changes the update rate of the auto-offset.
Must be set to default value.
1
The AD9985A only updates the PLL divide ratio when the LSBs are written to (Register 0x02).
2-WIRE SERIAL CONTROL REGISTER DETAIL CHIP
IDENTIFICATION
00
7–0
Chip Revision
An 8-bit register that represents the silicon revision.
PLL DIVIDER CONTROL
01
7–0
The 8 most significant bits of the 12-bit PLL divide
ratio PLLDIV. (The operational divide ratio is
PLLDIV + 1.)
PLL Divide Ratio MSBs
The PLL derives a master clock from an incoming
Hsync signal. The master clock frequency is then
divided by an integer value, such that the output is
phase-locked to Hsync. This PLLDIV value
determines the number of pixel times (pixels plus
horizontal blanking overhead) per line. This is
typically 20% to 30% more than the number of active
pixels in the display.
The 12-bit value of the PLL divider supports divide
ratios from 2 to 4095. The higher the value loaded in
this register, the higher the resulting clock frequency
with respect to a fixed Hsync frequency.
VESA has established some standard timing
specifications that assist in determining the value for
PLLDIV as a function of horizontal and vertical
display resolution and frame rate (Table 8).
However, many computer systems do not conform
precisely to the recommendations, and these numbers
should be used only as a guide. The display system
manufacturer should provide automatic or manual
means for optimizing PLLDIV. An incorrectly set
PLLDIV usually produces one or more vertical noise
bars on the display. The greater the error, the greater
the number of bars produced.
The power-up default value of PLLDIV is 1693
(PLLDIVM = 0x69, PLLDIVL = 0xDx).
The AD9985A updates the full-divide ratio only when
the LSBs are changed. Writing to the MSB by itself
does not trigger an update.
02
7–4 PLL Divide Ratio LSBs
The 4 least significant bits of the 12-bit PLL divide
ratio PLLDIV. The operational divide ratio is
PLLDIV + 1.
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| AD9985AKSTZ-140 | 110 MSPS/140 MSPS Analog Interface for Flat Panel Displays |
| AD9985BSTZ-110 | 110 MSPS/140 MSPS Analog Interface for Flat Panel Displays |
| AD9985 | 110 MSPS/140 MSPS Analog Interface for Flat Panel Displays |
| AD9985KSTZ-110 | 110 MSPS/140 MSPS Analog Interface for Flat Panel Displays |
| AD9985KSTZ-140 | 110 MSPS/140 MSPS Analog Interface for Flat Panel Displays |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| AD9985AKSTZ-140 | 功能描述:IC INTERFACE 8BIT 140MSPS 80LQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 專用 系列:- 特色產(chǎn)品:NXP - I2C Interface 標準包裝:1 系列:- 應用:2 通道 I²C 多路復用器 接口:I²C，SM 總線 電源電壓:2.3 V ~ 5.5 V 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應商設備封裝:16-TSSOP 包裝:剪切帶 (CT) 安裝類型:表面貼裝 產(chǎn)品目錄頁面:825 (CN2011-ZH PDF) 其它名稱:568-1854-1 |
| AD9985BST-110 | 制造商:Analog Devices 功能描述:110 MSPS/140 MSPS ANLG INTRFC FOR FLAT PNL DISPLAYS 80LQFP - Bulk |
| AD9985BSTZ-110 | 功能描述:IC INTERFACE 8BIT 110MSPS 80LQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 專用 系列:- 特色產(chǎn)品:NXP - I2C Interface 標準包裝:1 系列:- 應用:2 通道 I²C 多路復用器 接口:I²C，SM 總線 電源電壓:2.3 V ~ 5.5 V 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應商設備封裝:16-TSSOP 包裝:剪切帶 (CT) 安裝類型:表面貼裝 產(chǎn)品目錄頁面:825 (CN2011-ZH PDF) 其它名稱:568-1854-1 |
| AD9985KST-110 | 制造商:Analog Devices 功能描述:110 MSPS/140 MSPS ANLG INTRFC FOR FLAT PNL DISPLAYS 80LQFP - Bulk |
| AD9985KSTZ-110 | 功能描述:IC INTERFACE 8BIT 110MSPS 80LQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 專用 系列:- 特色產(chǎn)品:NXP - I2C Interface 標準包裝:1 系列:- 應用:2 通道 I²C 多路復用器 接口:I²C，SM 總線 電源電壓:2.3 V ~ 5.5 V 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應商設備封裝:16-TSSOP 包裝:剪切帶 (CT) 安裝類型:表面貼裝 產(chǎn)品目錄頁面:825 (CN2011-ZH PDF) 其它名稱:568-1854-1 |
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