參數(shù)資料
型號(hào)： AD9983AKCPZ-170
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 25/44頁(yè)
文件大?。?/td> 0K
描述： IC INTRFACE 8BIT 170MSPS 64LFCSP
標(biāo)準(zhǔn)包裝： 1
應(yīng)用： 視頻
接口： 模擬
電源電壓： 1.7 V ~ 3.47 V
封裝/外殼： 64-VFQFN 裸露焊盤(pán)，CSP
供應(yīng)商設(shè)備封裝： 64-LFCSP-VQ（9x9）
包裝： 管件
安裝類(lèi)型： 表面貼裝
AD9983A
Rev. 0 | Page 31 of 44
0x12—Bit[5] Hsync Input Polarity Override
This bit determines whether the chip selects the Hsync input
polarity or if it is specified. Setting this bit to 0 allows the chip
to automatically select the polarity of the input Hsync; setting it
to 1 indicates that Bit 4 of Register 0x12 specifies the polarity.
Power-up default is 0.
Table 20. Hsync Input Polarity Override Settings
Override Bit
Result
0
Hsync polarity determined by chip
1
Hsync polarity determined by user
Register 0x12, Bit 4
0x12—Bit[4] Hsync Input Polarity
If Bit 5 of Register 0x12 is 1, the value of this bit specifies the
polarity of the input Hsync. Setting this bit to 0 indicates an
active low Hsync; setting this bit to 1 indicates an active high
Hsync. Power-up default is 1.
Table 21. Hsync Input Polarity Settings
Hsync Polarity Bit
Result
0
Hsync input polarity is negative
1
Hsync input polarity is positive
0x12—Bit[3] Hsync Output Polarity
This bit sets the polarity of the Hsync output. Setting this bit to
0 sets the Hsync output to active low. Setting this bit to 1 sets
the Hsync output to active high. Power-up default setting is 1.
Table 22. Hsync Output Polarity Settings
Hsync Output
Polarity Bit
Result
0
Hsync output polarity is negative
1
Hsync output polarity is positive
0x13—Bits[7:0] Hsync Duration
An 8-bit register that sets the duration of the Hsync output
pulse. The leading edge of the Hsync output is triggered by the
internally-generated, phase-adjusted PLL feedback clock. The
AD9983A then counts a number of pixel clocks equal to the
value in this register. This triggers the trailing edge of the Hsync
output, which is also phase-adjusted.
VSYNC CONTROLS
0x14—Bit[7] Vsync Source Override
This is the active Vsync override. Setting this to 0 allows the
chip to determine the active Vsync source, setting it to 1 uses
Bit 6 of Register 0x14 to determine the active Vsync source.
Power-up default value is 0.
Table 23. Active Vsync Source Override
Override
Result
0
Vsync source determined by chip
1
Vsync source determined by user
Register 0x14, Bit 6
0x14—Bit[6] Vsync Source
This bit selects the source of the Vsync for sync processing only
if Bit 7 of Register 0x14 is set to 1. Setting Bit 6 to 0 specifies the
Vsync from the input pin; setting it to 1 selects Vsync from the
sync separator. Power-up default is 0.
Table 24. Active Vsync Select Settings
Select
Result
0
Vsync input
1
Vsync from sync separator
0x14—Bit[5] Vsync Input Polarity Override
This bit sets whether the chip selects the Vsync input polarity or
if it is specified. Setting this bit to 0 allows the chip to
automatically select the polarity of the input Vsync. Setting this
bit to 1 indicates that Bit 4 of Register 0x14 specifies the
polarity. Power-up default is 0.
Table 25. Vsync Input Polarity Override Settings
Override Bit
Result
0
Vsync polarity determined by chip
1
Vsync polarity determined by user
Register 0x14, Bit 4
0x14—Bit[4] Vsync Input Polarity
If Bit 5 of Register 0x14 is 1, the value of this bit specifies the
polarity of the input Vsync. Setting this bit to 0 indicates an
active low Vsync; setting this bit to 1 indicates an active high
Vsync. Power-up default is 1.
Table 26. Vsync Input Polarity Settings
Override Bit
Result
0
Vsync input polarity is negative
1
Vsync input polarity is positive
0x14—Bit[3] Vsync Output Polarity
This bit sets the polarity of the Vsync output. Setting this bit to
0 sets the Vsync output to active low. Setting this bit to 1 sets
the Vsync output to active high. Power-up default is 1.
Table 27. Vsync Output Polarity Settings
Vsync Output
Polarity Bit
Result
0
Vsync output polarity is negative
1
Vsync output polarity is positive
0x14—Bit[2] Vsync Filter Enable
This bit enables the Vsync filter allowing precise placement of
the Vsync with respect to the Hsync and facilitating the correct
operation of the Hsyncs/Vsync count.
Table 28. Vsync Filter Enable
Vsync Filter Bit
Result
0
Vsync filter disabled
1
Vsync filter enabled
相關(guān)PDF資料
PDF描述
VI-B42-IX-F4 CONVERTER MOD DC/DC 15V 75W
D38999/20MF11PB CONN RCPT 11POS WALL MNT W/PINS
VI-B42-IX-F2 CONVERTER MOD DC/DC 15V 75W
GRM1555C1H910JZ01D CAP CER 91PF 50V 5% NP0 0402
GRM1555C1H620JZ01D CAP CER 62PF 50V 5% NP0 0402
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AD9983AKCPZ-1701 制造商:AD 制造商全稱(chēng):Analog Devices 功能描述:High Performance 8-Bit Display Interface
AD9983AKSTZ-140 功能描述:IC DISPLAY 8BIT 140MSPS 80LQFP RoHS:是 類(lèi)別:集成電路 (IC) >> 接口 - 專(zhuān)用 系列:- 特色產(chǎn)品:NXP - I2C Interface 標(biāo)準(zhǔn)包裝:1 系列:- 應(yīng)用:2 通道 I²C 多路復(fù)用器 接口:I²C，SM 總線(xiàn) 電源電壓:2.3 V ~ 5.5 V 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:剪切帶 (CT) 安裝類(lèi)型:表面貼裝 產(chǎn)品目錄頁(yè)面:825 (CN2011-ZH PDF) 其它名稱(chēng):568-1854-1
AD9983AKSTZ-1401 制造商:AD 制造商全稱(chēng):Analog Devices 功能描述:High Performance 8-Bit Display Interface
AD9983AKSTZ-170 功能描述:IC DISPLAY 8BIT 170MSPS 80LQFP RoHS:是 類(lèi)別:集成電路 (IC) >> 接口 - 專(zhuān)用 系列:- 特色產(chǎn)品:NXP - I2C Interface 標(biāo)準(zhǔn)包裝:1 系列:- 應(yīng)用:2 通道 I²C 多路復(fù)用器 接口:I²C，SM 總線(xiàn) 電源電壓:2.3 V ~ 5.5 V 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:剪切帶 (CT) 安裝類(lèi)型:表面貼裝 產(chǎn)品目錄頁(yè)面:825 (CN2011-ZH PDF) 其它名稱(chēng):568-1854-1
AD9983AKSTZ-1701 制造商:AD 制造商全稱(chēng):Analog Devices 功能描述:High Performance 8-Bit Display Interface
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫(xiě)一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*