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參數(shù)資料
| 型號(hào)： | AD9983A/PCBZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 21/44頁 |
| 文件大?。?/td> | 0K |
| 描述： | KIT EVALUATION AD9983A |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | Advantiv® |
| 主要目的： | 視頻，視頻處理 |
| 嵌入式： | 否 |
| 已用 IC / 零件： | AD9983A |
| 主要屬性： | 3 x 8-Bit 140 MSPS ADC's |
| 次要屬性： | 集成式 PLL 和 VCO |
| 已供物品： | 板 |
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AD9983A
Rev. 0 | Page 28 of 44
Hex
Address
Read/Write,
Read Only
Bits
Default
Value
Register Name
Description
0x2C
R/W
7:5
000* ****
Offset Hold
Must be written to default for proper operation.
4
***0 ****
Auto-Offset Hold.
Disables the auto-offset and holds the feedback result.
0 = One time update
1 = Continuous update
3:0
**** 0000
Must be written to default for proper operation.
0x2D
R/W
7:0
1111 0000
TestReg5
Must be written to Reg. 0xE8 for proper operation.
0x2E
R/W
7:0
1111 0000
TestReg6
Must be written to Reg. 0xE0 for proper operation.
0x34
R/W
2
**** *0**
SOG Filter
SOG Filter Enable.
0 = Disable SOG filter
1 = Enable SOG filter
0x36
R/W
0
**** ***0
VCO Gear
VCO Gear adds another range to the VCO—used for lower
frequencies only.
0 = Disable low VCO gear
1 = Enable low VCO gear
0x3C
R/W
7:4
0000 ****
Auto Gain
Must be set to default for proper operation
3
**** 0***
Auto Gain Matching Hold
0 = Disables auto gain updates and holds the current auto offset
values.
1 = Allows auto gain to update continuously
2:0
**** *000
Auto Gain Matching Enable
000 = Auto gain is disabled
110= Auto gain is enabled
1 Functions with more than eight control bits, such as PLL divide ratio, gain, and offset, are only updated when the LSBs are written to (for example, Register 0x02 for
PLL divide ratio).
2 Gain registers (Register 0x05, Register 0x07, and Register 0x09) when written must each be followed with a write to their next register: Register 0x05 and Register 0x06,
Register 0x07, and Register 0x08, and Register 0x09 and Register 0x0A.
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