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參數資料
| 型號： | AD9975ABSTRL |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 調制器/解調器 |
| 英文描述： | Broadband Modem Mixed-Signal Front End |
| 中文描述： | MODEM-SUPPORT CIRCUIT, PQFP48 |
| 封裝： | 1.40 MM HEIGHT, PLASTIC, MS-026BBC, LQFP-48 |
| 文件頁數： | 16/20頁 |
| 文件大?。?/td> | 1392K |
| 代理商： | AD9975ABSTRL |
REV. 0
–16–
AD9975
INSTRUCTION BIT n
INSTRUCTION BIT n–1
SCLK
SDATA
t
DV
Figure 6. Timing Diagram Register Read from AD9975
MSB/LSB Transfers
The AD9975 serial port can support both most significant bit
(MSB) first or least significant bit (LSB) first data formats. The
bit order is controlled by the
SPI LSB First
Bit (Register 0, Bit 6).
The default value is 0, MSB first. Multibyte data transfers in
MSB format can be completed by writing an instruction byte
that includes the register address of the last address to be accessed.
The AD9975 will automatically decrement the address for each
successive byte required for the multibyte communication cycle.
When the
SPI LSB First
Bit (Register 0, Bit 6) is set high, the
serial port interprets both instruction and data bytes LSB first.
Multibyte data transfers in LSB format can be completed by
writing an instruction byte that includes the register address of
the first address to be accessed. The AD9975 will automatically
increment the address for each successive byte required for the
multibyte communication cycle.
Figures 7a and 7b show how the serial port words are built for
each of these modes.
SCLK
SDATA
SENABLE
INSTRUCTION CYCLE
DATA TRANSFER CYCLE
R/W
I6(n)I5(n)
I4
I3
I2
I1
I0
D7n
D6n
D6n
D7n
Figure 7a. Serial Register Interface Timing MSB First
SCLK
SDATA
SENABLE
INSTRUCTION CYCLE
DATA TRANSFER CYCLE
I0
I1
I2
I3
I4
I5(n)I6(n)
D00
D10
D20
D6n
D7n
R/W
Figure 7b. Serial Register Interface Timing LSB First
Notes on Serial Port Operation
The serial port is disabled and all registers are set to their default
values during a hardware reset. During a software reset, all regis-
ters except Register 0 are set to their default values. Register 0
will remain at the last value sent, with the exception that the
Software Reset
Bit will be set to 0.
Table V. Register Layout
Address
(hex)
Default
(hex)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Type
00
Select 4-Wire LSB/MSB
SPORT
Software
Reset
00
R/W
First
01
Power-
Down
PLL-A
Power-
Down
DAC
Power-Down Power-Down Power-
Interpolators RX Reference Down ADC Receive Filter
Power-Down 00
R/W
and SPGA
and CPGA
02
00
R/W
03
ADC Clock
Source
OSC IN/2
PLL-A (xL)
Multiplier [1:0]
01
R/W
04
RX LPF
Tuning
Update
Disable
RX LPF
Tuning
Update in
Progress
RX Path
DC Offset HPF
Correction Bypass
RX Digital Fast ADC
Wideband RX Enable
LPF
RX LPF
Bypass
01
R/W
Sampling
1-Pole
RX LPF
05
RX LPF Filter Tuning Target [7:0]
80
R/W
06
RXBOOST
Active Low
RXBOOST PGA Gain
RX PGA Gain [4:0]
00
R/W
Setting
through
Register
07
TX Interpolation Filter Select
Sample TX TX Data
on Falling
TXCLKIN Complement
10
R/W
Input Twos
08
CLK-B Equal CLK-A
to OSC IN/4
CLK-B
Output
CLK-A
Output
Disable
Three-State
RX Port
ADC Output RX Data
on Falling
RXCLK
00
R/W
Equal
to OSC IN Disable
Output Twos
Complement
0F
Version [3:0]
00
R
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