參數(shù)資料
型號(hào): AD9978
廠商: Analog Devices, Inc.
英文描述: Dual-Channel, 14-Bit CCD Signal Processor with Precision Timing Core
中文描述: 雙通道,14位CCD信號(hào)處理器核心的精密計(jì)時(shí)
文件頁(yè)數(shù): 1/2頁(yè)
文件大?。?/td> 67K
代理商: AD9978
Dual-Channel, 14-Bit CCD Signal
Processor with
Precision Timing
Core
AD9978
FEATURES
Rev. SpA
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
2007 Analog Devices, Inc. All rights reserved.
www.analog.com
Dual AFE channels
1.8 V analog and digital core supply voltage
Serial data output with reduced range LVDS outputs
Differential analog inputs
CDS or SHA configuration (CDS bypass) with
3 dB, 0 dB, +3 dB, and +6 dB gain
6 dB to 42 dB, 10-bit variable gain amplifier (VGA)
14-bit, 65 MHz analog-to-digital converter (ADC)
Black level clamp with variable level control
Precision Timing
core with 240 ps resolution @ 65 MHz
APPLICATIONS
Digital video cameras
Digital still cameras
Digital copiers
Multifunction printers
High speed industrial cameras
GENERAL DESCRIPTION
The AD9978 is a highly integrated, dual-channel, CCD signal
processor for high speed digital video camera applications. Each
channel is specified at pixel rates of up to 65 MHz and consists
of a complete analog front end with ADC conversion. The
Precision Timing
core allows adjustment of the correlated
double sampler (CDS) and sample-and-hold amplifier (SHA)
clocks with 240 ps resolution at 65 MHz operation. The
AD9978 also contains a reduced range, low voltage differential
signaling (LVDS) interface for the dual-channel data outputs.
Each analog front end includes black level clamping, a CDS,
a VGA, and a 65 MHz, 14-bit ADC. Operation is programmed
using a 3-wire serial interface.
Packaged in a space-saving, 6 mm × 6 mm, 40-lead LFCSP, the
AD9978 is specified over an operating temperature range of
25°C to +85°C.
FUNCTIONAL BLOCK DIAGRAM
INP_A
INM_A
INM_B
INP_B
–3dB, 0dB, +3dB, +6dB
–3dB, 0dB, +3dB, +6dB
CDS/
SHA
VGA
6dB TO 42dB
CLAMP
ADC
VD
HD
SDATA
SCK
CLI
CLK_OUT
DOUT0P
DOUT0N
DOUT1P
DOUT1N
TCLKP
TCLKN
DOUT2P
DOUT2N
DOUT3P
DOUT3N
SL
CLAMP
VREF
ADC
6dB TO 42dB
CDS/
SHA
VGA
PRECISION
TIMING
CORE
SYNC
GENERATOR
INTERNAL CLOCKS
INTERNAL
REGISTERS
LVDS
SERIALIZER
AD9978
0
Figure 1.
For more information about the AD9978, contact Analog Devices via email at
afe.ccd@analog.com
.
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