參數(shù)資料
型號： AD9958BCPZ
廠商： ANALOG DEVICES INC
元件分類： 模擬信號調(diào)理
英文描述： 2-Channel 500 MSPS DDS with 10-Bit DACs
中文描述： SPECIALTY ANALOG CIRCUIT, QCC56
封裝： 8 X 8 MM, LEAD FREE, MO-220-VLLD-2, LFCSP-56
文件頁數(shù)： 35/40頁
文件大?。?/td> 1051K
代理商： AD9958BCPZ
AD9958
CHANNEL REGISTER MAP
Table 28.
Register Name
(Address)
Channel
Function
1
(CFR)
(0x03)
Rev. 0 | Page 35 of 40
Bit
Range
<7:0>
Bit 7 (MSB)
Digital power-
down
Bit 6
DAC
power
down
Bit 5
Matched
pipe delays
active
Bit 4
Auto clear
sweep
accumulator
Bit 3
Clear sweep
accumulator
Bit 2
Auto clear
phase
accumulator
Bit 1
Clear phase
accumulator
2
(LSB)
Bit 0
Sine
wave
output
enable
Defaul
t Value
0x02
<15:8>
Linear sweep
no-dwell
Linear
sweep
enable
Load SRR
at I/O
Update
Open
Open
Must be 0
DAC full-scale current
control <9:8>
0x03
<23:16>
Amplitude freq. phase
select <23:22>
Open <21:16>
0x00
<7:0>
<15:8>
<23:16>
<31:24>
<7:0>
<15:8>
Frequency Tuning Word 0 <7:0>
Frequency Tuning Word 0 <15:8>
Frequency Tuning Word 0 <23:16>
Frequency Tuning Word 0 <31:24>
Phase Offset Word 0
0x00
0x00
0x00
Channel
Frequency Tuning
Word 0
1
(CTW0)
(0x04)
Channel Phase
1
Offset Word 0
(CPW0) (0x05)
Amplitude
Control (ACR)
(0x06)
Open <15:14>
Phase Offset Word 0 <13:8>
<7:0>
<15:8>
Amplitude scale factor
Amplitude
multiplier
enable
Amplitude ramp rate <23:16>
Linear sweep rising ramp rate (RSRR) <7:0>
Linear sweep falling ramp rate (FSRR) <15:8>
0x00
0x00
Increment/decrement
step size <15:14>
Open
Ramp-up/
ramp-down
enable
Load ARR at I/O
update
Amplitude scale
factor <9:8>
<23:16>
<7:0>
<15:8>
–
–
–
Linear Sweep
Ramp Rate
1
(LSR)
(0x07)
LSR Rising Delta
1
(RDW) (0x08)
LSR Falling Delta
1
(FDW) (0x09)
1
There are two sets of channel registers and profile registers, one per channel. This is not shown in the channel or profile register maps because the addresses of all
channel registers and profile registers are the same for each channel. Therefore, the channel enable bits determine if the channel’s channel registers and/or profile
registers are written to or not.
2
The clear accumulator bit is set to Logic 1 after a master reset. It self clears or is set to Logic 0 when an I/O update is asserted.
PROFILE REGISTER MAP
Table 29.
(MSB)
Bit 7
Bit 6
Bit 5
Channel Word 1 (CTW1) (0x0A)
<31:0>
Freq. tuning word <31:0> or phase word <31:18> or amplitude word <31:22>
Channel Word 2 (CTW2) (0x0B)
<31:0>
Freq. tuning word <31:0> or phase word <31:18> or amplitude word <31:22>
Channel Word 3 (CTW3) (0x0C)
<31:0>
Freq. tuning word <31:0> or phase word <31:18> or amplitude word <31:22>
Channel Word 3 (CTW4) (0x0D)
<31:0>
Freq. tuning word <31:0> or phase word <31:18> or amplitude word <31:22>
Channel Word 5 (CTW5) (0x0E)
<31:0>
Freq. tuning word <31:0> or phase word <31:18> or amplitude word <31:22>
Channel Word 6 (CTW6) (0x0F)
<31:0>
Freq. tuning word <31:0> or phase word <31:18> or amplitude word <31:22>
Channel Word 7 (CTW7) (0x10)
<31:0>
Freq. tuning word <31:0> or phase word <31:18> or amplitude word <31:22>
Channel Word 8 (CTW8) (0x11)
<31:0>
Freq. tuning word <31:0> or phase word <31:18> or amplitude word <31:22>
Channel Word 9 (CTW9) (0x12)
<31:0>
Freq. tuning word <31:0> or phase word <31:18> or amplitude word <31:22>
Channel Word 10 (CTW10) (0x13)
<31:0>
Freq. tuning word <31:0> or phase word <31:18> or amplitude word <31:22>
Channel Word 11 (CTW11) (0x14)
<31:0>
Freq. Tuning Word <31:0> or phase word <31:18> or amplitude word <31:22>
Channel Word 12 (CTW12) (0x15)
<31:0>
Freq. Tuning Word <31:0> or phase word <31:18> or amplitude word <31:22>
Channel Word 13 (CTW13) (0x16)
<31:0>
Freq. tuning word <31:0> or phase word <31:18> or amplitude word <31:22>
Channel Word 14 (CTW14) (0917)
<31:0>
Freq. tuning word <31:0> or phase word <31:18> or amplitude word <31:22>
Channel Word 15 (CTW15) (0x18)
<31:0>
Freq. tuning word <31:0> or phase word <31:18> or amplitude word <31:22>
<7:0>
Rising delta word <7:0>
–
<15:8>
<23:16>
<31:24>
<7:0>
Rising delta word <15:8>
Rising delta word <23:16>
Rising delta word <31:24>
Falling delta word <7:0>
–
–
–
–
<15:8>
<23:16>
<31:24>
Falling delta word <15:8>
Falling delta word <23:16>
Falling delta word <31:24>
–
–
–
Register Name (address)
Bit Range
Bit 4
Bit 3
Bit 2
Bit 1
(LSB)
Bit 0
Default
Value
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
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