參數資料
型號: AD9958BCPZ
廠商: ANALOG DEVICES INC
元件分類: 模擬信號調理
英文描述: 2-Channel 500 MSPS DDS with 10-Bit DACs
中文描述: SPECIALTY ANALOG CIRCUIT, QCC56
封裝: 8 X 8 MM, LEAD FREE, MO-220-VLLD-2, LFCSP-56
文件頁數: 25/40頁
文件大?。?/td> 1051K
代理商: AD9958BCPZ
AD9958
Rev. 0 | Page 25 of 40
FTW0
SINGLE–TONE
MODE
LINEAR SWEEP MODE ENABLE, NO-DWELL BIT SET
FTW1
A
A
A
B
B
B
F
OUT
TIME
PS<2> = 1 PS<2> = 0
PS<2> = 0
PS<2> = 1
PS<2> = 1
PS<2> = 0
0
Figure 37.
FTW0
SINGLE–TONE
MODE
LINEAR SWEEP MODE
AT POINT A: LOAD RISING RAMP RATE REGISTER, APPLY RISING DFTW.
AT POINT B: LOAD FALLING RAMP RATE REGISTER, APPLY FALLING DFTW.
PS<2> = 1
PS<2> = 0
PS<2> = 0
TIME
FTW1
A
B
F
OUT
0
Figure 38. Linear Sweep with the No-Dwell Feature Disabled
SWEEP AND PHASE ACCUMULATOR CLEARING
FUNCTIONS
The AD9958 allows two different clearing functions. The first
is a continuous zeroing of the sweep logic and phase accumu-
lator (clear and hold). The second is a clear and release or
automatic zeroing function. CFR <4> is the automatic clear
sweep accumulator bit and CFR <2> is the automatic clear
phase accumulator bit. The continuous clear bits are located in
CFR, where CFR <3> clears the sweep accumulator and
CFR <1> clears the phase accumulator.
Continuous Clear Bits
The continuous clear bits are static control signals that, when
active high, hold the respective accumulator at 0 while the bit is
active. When the bit goes low, the respective accumulator is
allowed to operate.
Clear and Release Bits
The auto clear sweep accumulator bit, when set, clears and
releases the sweep accumulator upon an I/O update or a change
in the profile input pins. The auto clear phase accumulator,
when set, clears and releases the phase accumulator upon an
I/O update or a change in the profile pins. The automatic clear-
ing function is repeated for every subsequent I/O update or
change in profile pins until the clear and release bits are reset
via the serial port.
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