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參數(shù)資料
| 型號： | AD9957BSVZ-REEL |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 通信及網(wǎng)絡(luò) |
| 英文描述： | 1 GSPS Quadrature Digital Upconverter with 18-Bit IQ Data Path and 14-Bit DAC |
| 中文描述： | SPECIALTY TELECOM CIRCUIT, PQFP100 |
| 封裝： | ROHS COMPLIANT, MS-026AED-HD, TQFP-100 |
| 文件頁數(shù)： | 52/60頁 |
| 文件大?。?/td> | 840K |
| 代理商： | AD9957BSVZ-REEL |
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AD9957
Bit
No.
11
Rev. 0 | Page 52 of 60
Mnemonic
PDCLK Enable
Description
0: the PDCLK pin is disabled and forced to a static Logic 0 state; the internal clock signal continues to operate
and provide timing to the data assembler.
1: the internal PDCLK signal appears at the PDCLK pin (default).
0: normal PDCLK polarity; Q-data associated with Logic 1, I-data with Logic 0 (default).
1: inverted PDCLK polarity.
0: normal TxEnable polarity; Logic 0 is standby, Logic 1 is transmit (default).
1: inverted TxEnable polarity; Logic 0 is transmit, Logic 1 is standby.
0: an I/Q data pair is delivered as I-data first followed by Q-data (default).
1: an I/Q data pair is delivered as Q-data first followed by I-data.
0: simultaneous application of amplitude, phase and frequency changes to the DDS arrive at the output in
the order listed (default).
1: simultaneous application of amplitude, phase and frequency changes to the DDS arrive at the output
simultaneously.
Ineffective when CFR1 Bits<25:24> = 01b.
0: when the TxENABLE pin is false, the data assembler ignores the input data and internally forces zeros on
the baseband signal path (default).
1: when the TXENABLE pin is false, the data assembler ignores the input data and internally forces the last
value received on the baseband signal path.
0: enables the SYNC_SMP_ERR pin to indicate (active high) detection of a synchronization pulse
sampling error.
1: the SYNC_SMP_ERR pin is forced to a static Logic 0 condition (default).
10
PDCLK Invert
9
TxEnable Invert
8
Q First Data
Pairing
Matched Latency
Enable
7
6
Data Assembler
Hold Last Value
5
Sync Timing
Validation Disable
4:0
Not Available
Control Function Register 3 (CFR3)
Address 0x02, four bytes are assigned to this register.
Table 20. Bit Descriptions for CFR3 Register
Bit
No.
Mnemonic
31:30
DRV0
29:27
Not Available
26:24
VCO SEL
23:22
Not Available
21:19
I
CP
18:16
Not Available
15
REFCLK Input
Divider Bypass
14
REFCLK Input
Divider ResetB
13:9
Not Available
8
PLL Enable
Description
Controls REFCLK_OUT pin (see Table 7 for details); default is 00b.
Selects frequency band of the VCO in the REFCLK PLL (see Table 9 for details); default is 111b.
Selects the charge pump current in the REFCLK PLL (see Table 9 for details); default is 111b.
0: input divider is selected (default).
1: input divider is bypassed.
0: input divider is reset.
1: input divider operates normally (default).
0: REFCLK PLL bypassed (default).
1: REFCLK PLL enabled.
This 7-bit number is divide modulus of the REFCLK PLL feedback divider; default is 0000000b.
7:1
0
N
Not Available
Auxiliary DAC Control Register
Address 0x03, four bytes are assigned to this register.
Table 21. Bit Descriptions for Auxiliary DAC Control Register
Bit(s)
Mnemonic
Description
31:8
Not Available
7:0
FSC
This 8-bit number controls the full-scale output current of the main DAC (see the Auxiliary DAC section);
default is 0xFF.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
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| AD9957BSVZREEL13 | 制造商:AD 制造商全稱:Analog Devices 功能描述:1 GSPS Quadrature Digital Upconverter w/18-Bit IQ Data Path and 14-Bit DAC |
| AD9958 | 制造商:AD 制造商全稱:Analog Devices 功能描述:2-Channel 500 MSPS DDS with 10-Bit DACs |
| AD9958 PCB | 制造商:Analog Devices 功能描述:EVAL BOARD ((NS)) |
| AD9958/PCB | 制造商:Analog Devices 功能描述:Evaluation Board For 2-Channel 500 MSPS DDS With 10-Bit DACs 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Analog Devices 功能描述:IC 10-BIT DAC DDS |
| AD9958/PCBZ | 功能描述:BOARD EVALUATION FOR AD9958 RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評估演示板和套件 系列:AgileRF™ 標(biāo)準(zhǔn)包裝:1 系列:PSoC® 主要目的:電源管理，熱管理 嵌入式:- 已用 IC / 零件:- 主要屬性:- 次要屬性:- 已供物品:板，CD，電源 |
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