參數(shù)資料
型號: AD9957BSVZ-REEL
廠商: ANALOG DEVICES INC
元件分類: 通信及網(wǎng)絡
英文描述: 1 GSPS Quadrature Digital Upconverter with 18-Bit IQ Data Path and 14-Bit DAC
中文描述: SPECIALTY TELECOM CIRCUIT, PQFP100
封裝: ROHS COMPLIANT, MS-026AED-HD, TQFP-100
文件頁數(shù): 17/60頁
文件大?。?/td> 840K
代理商: AD9957BSVZ-REEL
AD9957
BLACKFIN INTERFACE (BFI)
A subset of the QDUC mode is the Blackfin interface (BFI)
mode, shown in Figure 27; grayed items are inactive. In this
mode, a separate I and Q serial bit stream is applied to the
baseband data port instead of parallel data-words. The two
serial inputs provide for 16-bit I- and Q-words (unlike the 18-
bit words in normal QDUC mode). The serial bit streams are
delivered to the Blackfin interface. The Blackfin interface
converts the 16-bit serial data into 16-bit parallel data to
propagate down the signal processing chain.
Rev. 0 | Page 17 of 60
The Blackfin interface includes an additional pair of half-band
filters in both I and Q signal paths
(not shown explicitly in the
diagram). The two half-band filters increase the interpolation of
the baseband data by a factor of four, relative to the normal
QDUC mode.
The synchronization of the serial data occurs through the
PDCLK signal. In BFI mode, the PDCLK signal is effectively
the bit clock for the serial data.
0
PDCLK
I/Q IN
E
DAC_RSET
IOUT
IOUT
TxENABLE
DAC GAIN
θ
cos (
ω
t+
θ
)
I
S
F
CLOCK
F
P
8
SYSCLK
PLL
÷2
C
REF_CLK
REF_CLK
REFCLK_OUT
XTAL_SEL
AD9957
ω
sin (
ω
t+
θ
)
S
S
P
P
M
2
2
DDS
AUX
DAC
8-BIT
POWER
DOWN
CONTROL
2
D
I
Q
IS
QS
B
18
18
16
16
I
C
I
C
OSK
INTERNAL CLOCK TIMING AND CONTROL
DAC
14-BIT
C
O
FTW
PW
PARALLEL DATA
TIMING AND CONTROL
2
R
RAM
P
C
I
S
S
SERIAL I/O
PORT
I
PROGRAMMING
REGISTERS
3
I Q
IS QS
H
F
C
(
H
F
C
(
OUTPUT
SCALE
FACTOR
Figure 27. Quadrature Modulation Mode, Blackfin Interface
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