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參數(shù)資料
| 型號： | AD9956YCPZ1 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | 2.7 GHz DDS-Based AgileRF |
| 中文描述： | 2.7千兆赫基于DDS的AgileRF |
| 文件頁數(shù)： | 31/32頁 |
| 文件大?。?/td> | 805K |
| 代理商： | AD9956YCPZ1 |
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AD9956
CFR2<15:12> PLLREF Divider Control Bits (÷M)
These 4 bits set the PLLREF divider (÷M) ratio where
M
is a
value equal to 1 to 16. CFR2<15:12> = 0000 means that M = 1
and CFR2<15:12> = 1111 means that M = 16, or simply, M =
CFR2<15:12> + 1.
Rev. 0 | Page 31 of 32
CFR2<15:12> =
0000
0001
0010
0011
0100
0101
0110
0111
M =
1
2
3
4
5
6
7
8
CFR2<15:12> =
1000
1001
1010
1011
1100
1101
1110
1111
M =
9
10
11
12
13
14
15
16
CFR2<11:8> PLLREF Divider Control Bits (÷N)
These 4 bits set the PLLOSC divider (÷N) ratio where N is a
value equal to 1 to 16. CFR2<11:8> = 0000 means that N = 1
and CFR2<11:8> = 1111 means that N = 16, or N =
CFR2<11:8> + 1.
CFR2<15:12> =
0000
0001
0010
0011
0100
0101
0110
0111
N =
1
2
3
4
5
6
7
8
CFR2<11:8> =
1000
1001
1010
1011
1100
1101
1110
1111
N =
9
10
11
12
13
14
15
16
CFR2<7:6> Open
Unused locations. Write a Logic 0.
CFR2<5> CP Polarity
This bit sets the polarity of the charge pump, in response to a
ground referenced or a supply referenced VCO.
CFR2<5> = 0 (default). The charge pump is configured to
operate with a supply referenced VCO. If PLLOSC lags PLLREF,
the charge pump will attempt to drive the VCO control node
voltage higher. If PLLOSC leads PLLREF, the charge pump will
attempt to drive the VCO control node voltage lower.
CFR2<5> = 1. The charge pump is configured to operate with a
ground referenced VCO. If PLLOSC lags PLLREF, the charge
pump will attempt to drive the VCO control node voltage lower.
If PLLOSC leads PLLREF, the charge pump will attempt to drive
the VCO control node voltage higher.
CFR2<4> Charge Pump Full Power-Down
This bit, when set, will put the charge pump into a full power-
down mode.
CFR2<4> = 0 (default). The charge pump is powered on and
operating normally.
CFR2<4> = 1. The charge pump is completely powered down.
CFR2<3> Charge Pump Quick Power-Down
Rather than power down the charge pump, which can take a
long time to recover from, a quick power-down mode, which
powers down only the charge pump output buffer, is included.
While this doesn’t reduce the power consumption significantly,
it does shut off the output to the charge pump and allows it to
come back on in a rapidly.
CFR2<3> = 0 (default). The charge pump is powered on and
operating normally.
CFR2<3> = 1. The charge pump is on and running, but the
output buffer is powered down.
CFR2<2:0> Charge Pump Current Scale.
A base output current from the charge pump is determined by a
resistor connected from the CP_RSET pin to ground (see the
PLL Circuitry section). However, it is possible to multiply the
charge pump output current by a value from 1:8 by programming
these bits. The charge pump output current are scaled by
CFR2<2:0> +1.
CFR2<2:0> = 000 (default). Scale factor = 1 to CFR2<2:0> = 111 (8).
CFR2<2:0>
000
001
010
011
100
101
110
111
Scale Factor
1
2
3
4
5
6
7
8
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相關(guān)代理商/技術(shù)參數(shù) |
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| AD9956YCPZ-REEL1 | 制造商:AD 制造商全稱:Analog Devices 功能描述:2.7 GHz DDS-Based AgileRF |
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