- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄16826 > AD9956/PCBZ (Analog Devices Inc)BOARD EVAL FOR AD9956 PDF資料下載
參數(shù)資料
| 型號： | AD9956/PCBZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 4/32頁 |
| 文件大小： | 0K |
| 描述： | BOARD EVAL FOR AD9956 |
| 產(chǎn)品培訓(xùn)模塊： | Direct Digital Synthesis Tutorial Series (1 of 7): Introduction Direct Digital Synthesizer Tutorial Series (7 of 7): DDS in Action Direct Digital Synthesis Tutorial Series (3 of 7): Angle to Amplitude Converter Direct Digital Synthesis Tutorial Series (6 of 7): SINC Envelope Correction Direct Digital Synthesis Tutorial Series (4 of 7): Digital-to-Analog Converter Direct Digital Synthesis Tutorial Series (2 of 7): The Accumulator |
| 標準包裝： | 1 |
| 系列： | AgileRF™ |
| 主要目的： | 計時，直接數(shù)字合成（DDS） |
| 已用 IC / 零件： | AD9956 |
| 已供物品： | 板 |
| 相關(guān)產(chǎn)品： | AD9956YCPZ-ND - IC SYNTHESIZER 1.8V 48LFCSP AD9956YCPZ-REEL7-ND - IC SYNTHESIZER 1.8V 48LFCSP |
第1頁第2頁第3頁當前第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁
AD9956
Rev. A | Page 12 of 32
Table 3. 48-Lead LFCSP Pin Function Description
Pin No.
Mnemonic
Description
1, 3, 8, 26, 30,
34, 37, 43, 49
AGND
Analog Ground.
2, 4, 7, 27, 38,
44, 48
AVDD
Analog Core Supply (1.8 V).
5
IOUT
DAC Analog Output.
6
IOUT
DAC Analog Complementary Output.
9
I/O_RESET
Resets the serial port when synchronization is lost in communications but does not reset the de-
vice itself (ACTIVE HIGH). When not being used, this pin should be forced low, because it floats to
the threshold value.
10
RESET
Master RESET. Clears all accumulators and returns all registers to their default values (ACTIVE
HIGH).
11, 25
DVDD
Digital Core Supply (1.8 V).
12, 24
DGND
Digital Ground.
13
SDO
Serial Data Output. Used only when device is programmed for 3-wire serial data mode.
14
SDI/O
Serial Data I/O. When the part is programmed for 3-wire serial data mode, this is input only; in
2-wire mode, it serves as both the input and output.
15
SCLK
Serial Data Clock. Provides the clock signal for the serial data port.
16
CS
Active Low Signal That Enables Shared Serial Busses. When brought high, the serial port ignores
the serial data clocks.
17
DVDD_I/O
Digital Interface Supply (3.3 V).
18
SYNC_OUT
Synchronization Clock Output.
19
PLL_LOCK/SYNC_IN
Bidirectional Dual Function Pin. Depending on device programming, it is either the DDS’ synchro-
nization input (allows alignment of multiple subclocks) or the PLL lock detect output signal.
20
I/O_UPDATE
This input pin, when set high, transfers the data from the I/O buffers to the internal registers on the
rising edge of the internal SYNC_CLK, which can be observed on SYNC_OUT.
21 to 23
PS0 to PS2
Profile Select Pins. Specify one of eight frequency tuning word/phase offset word profiles. In linear
sweep mode, PS0 determines the state of the sweep. In linear sweep no dwell mode, PS0 is a trig-
ger that initiates the sweep. PS1 and PS2 have no function during linear sweep mode or linear
sweep no dwell mode.
28
REFCLK
RF Divider and DDS REFCLK Complementary Input.
29
REFCLK
RF Divider and DDS REFCLK Input.
32
DRV
CML Driver Complementary Output.
33
DRV
CML Driver Output.
31, 35
CP_VDD
Charge Pump Supply Pin (3.3 V). To minimize noise on the charge pump, isolate this supply from
DVDD_I/O.
36
CP_OUT
Charge Pump Output.
39
PLLREF
Phase Frequency Detector Reference Input.
40
PLLREF
Phase Frequency Detector Reference Complementary Input.
41
PLLOSC
Phase Frequency Detector Oscillator (Feedback) Complementary Input.
42
PLLOSC
Phase Frequency Detector Oscillator (Feedback) Input.
45
CP_RSET
Charge Pump Current Set (Program Charge Pump Current with a Resistor to AGND).
46
DRV_RSET
CML Driver Output Current Set (Program CML Output Current with a Resistor to AGND).
47
DAC_RSET
DAC Output Current Set (Program DAC Output Current with a Resistor to AGND).
Note that the exposed paddle on this package is an electrical connection (Pin 49) as well as a thermal enhancement. In order for the
device to function properly, the paddle MUST be attached to analog ground.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| 0210391089 | CABLE JUMPER 1MM .203M 37POS |
| 570-003-744-200 | ASSEMBLY RECEPT 3POS WATERPROOF |
| 362A024-4/42-0 | BOOT MOLDED |
| 570-003-734-100 | ASSEMBLY PLUG 3POS WATERPROOF |
| KSZ8864RMN-EVAL | BOARD EVALUATION FOR KSZ8864RMN |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD9956-VCO/PCB | 制造商:Analog Devices 功能描述:EVAL BD FOR AD9956, 2.7 GHZ DDS-BASED AGILERF SYNTHESIZER - Trays 制造商:Analog Devices 功能描述:EVAL CARD ((NS)) |
| AD9956-VCO/PCBZ | 功能描述:BOARD EVAL 14BIT 1.8V 48LFCSP RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評估演示板和套件 系列:AgileRF™ 標準包裝:1 系列:PSoC® 主要目的:電源管理，熱管理 嵌入式:- 已用 IC / 零件:- 主要屬性:- 次要屬性:- 已供物品:板，CD，電源 |
| AD9956XCPZ | 制造商:Analog Devices 功能描述:DGTL SYNTHESIZER 48LFCSP EP - Tape and Reel |
| AD9956YCP | 制造商:Analog Devices 功能描述:- Trays |
| AD9956YCPZ | 功能描述:IC SYNTHESIZER 1.8V 48LFCSP RoHS:是 類別:集成電路 (IC) >> 接口 - 直接數(shù)字合成 (DDS) 系列:- 產(chǎn)品變化通告:Product Discontinuance 27/Oct/2011 標準包裝:2,500 系列:- 分辨率（位）:10 b 主 fclk:25MHz 調(diào)節(jié)字寬（位）:32 b 電源電壓:2.97 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:帶卷 (TR) |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。