參數資料
| 型號： | AD9949KCPZ |
| 廠商： | Analog Devices Inc |
| 文件頁數： | 11/36頁 |
| 文件大小： | 0K |
| 描述： | IC CCD SIGNAL PROCESSOR 40-LFCSP |
| 標準包裝： | 1 |
| 類型： | CCD 信號處理器，12 位 |
| 輸入類型： | 邏輯 |
| 輸出類型： | 邏輯 |
| 接口： | 3 線串口 |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 40-VFQFN 裸露焊盤，CSP |
| 供應商設備封裝： | 40-LFCSP |
| 包裝： | 托盤 |
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AD9949
Rev. B | Page 19 of 36
Table 16. H1CONTROL, RGCONTROL, DRVCONTROL, and SAMPCONTROL Register Parameters
Parameter
Length
Range
Description
Polarity
1b
High/Low
Polarity Control for H1/H3 and RG (0 = No Inversion, 1 = Inversion).
Positive Edge
6b
0 to 47 Edge Location
Positive Edge Location for H1/H3 and RG.
Negative Edge
6b
0 to 47 Edge Location
Negative Edge Location for H1/H3 and RG.
Sample Location
6b
0 to 47 Sample Location
Sampling Location for SHP and SHD.
Drive Control
3b
0 to 7 Current Steps
Drive Current for H1 to H4 and RG Outputs, 0 to 7 Steps of 4.1 mA Each.
DOUT Phase
6b
0 to 47 Edge Location
Phase Location of Data Outputs with Respect to Pixel Period.
Table 17. Precision Timing Edge Locations
Quadrant
Edge Location (Decimal)
Register Value (Decimal)
Register Value (Binary)
I
0 to 11
000000 to 001011
II
12 to 23
16 to 27
010000 to 011011
III
24 to 35
32 to 43
100000 to 101011
IV
36 to 47
48 to 59
110000 to 111011
H-DRIVER AND RG OUTPUTS
In addition to the programmable timing positions, the AD9949 features on-chip output drivers for the RG and H1 to H4 outputs. These
drivers are powerful enough to directly drive the CCD inputs. The H-driver and RG driver current can be adjusted for optimum rise/fall
time into a particular load by using the DRVCONTROL register (Address 0×62). The DRVCONTROL register is divided into five differ-
ent 3-bit values, each one being adjustable in 4.1 mA increments. The minimum setting of 0 is equal to OFF or three-state, and the maxi-
mum setting of 7 is equal to 30.1 mA.
As shown in Figure 18, the H2/H4 outputs are inverses of H1/H3. The internal propagation delay resulting from the signal inversion is
less than l ns, which is significantly less than the typical rise time driving the CCD load. This results in a H1/H2 crossover voltage at ap-
proximately 50% of the output swing. The crossover voltage is not programmable.
DIGITAL DATA OUTPUTS
The AD9949 data output phase is programmable using the DOUTPHASE register (Address 0×64). Any edge from 0 to 47 may be pro-
grammed, as shown in Figure 19. The pipeline delay for the digital data output is shown in Figure 20.
FIXED CROSSOVER VOLTAGE
H1/H3
H2/H4
tPD
H2/H4
H1/H3
tRISE
tPD << tRISE
03751-019
Figure 18. H-Clock Inverse Phase Relationship
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| AD9949KCPZRL | 功能描述:IC CCD SIGNAL PROCESSOR 40-LFCSP RoHS:是 類別:集成電路 (IC) >> 接口 - 傳感器和探測器接口 系列:- 其它有關文件:Automotive Product Guide 產品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:74 系列:- 類型:觸控式傳感器 輸入類型:數字 輸出類型:數字 接口:JTAG，串行 電流 - 電源:100µA 安裝類型:表面貼裝 封裝/外殼:20-TSSOP（0.173"，4.40mm 寬） 供應商設備封裝:20-TSSOP 包裝:管件 |
| AD9950KJ | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Parallel-Input Frequency Synthesizer |
| AD9950TJ | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Parallel-Input Frequency Synthesizer |
| AD9951 | 制造商:AD 制造商全稱:Analog Devices 功能描述:400 MSPS 14-Bit, 1.8 V CMOS Direct Digital Synthesizer |
| AD9951/PCBZ | 制造商:Analog Devices 功能描述:AD9951 400 MSPS DDS W/ 14 BIT DAC EVALBD - Boxed Product (Development Kits) |
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