參數(shù)資料
型號(hào)： AD9948KCPZ
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 9/28頁(yè)
文件大?。?/td> 0K
描述： IC CCD SIGNAL PROCESSOR 40-LFCSP
標(biāo)準(zhǔn)包裝： 1
類(lèi)型： CCD 信號(hào)處理器，10 位
輸入類(lèi)型： 邏輯
輸出類(lèi)型： 邏輯
接口： 3 線串口
安裝類(lèi)型： 表面貼裝
封裝/外殼： 40-VFQFN 裸露焊盤(pán)，CSP
供應(yīng)商設(shè)備封裝： 40-LFCSP
包裝： 托盤(pán)
REV. 0
AD9948
–17–
HD
HBLK
. . .
THE POLARITY OF H1 DURING BLANKING IS PROGRAMMABLE (H2 IS OPPOSITE POLARITY OF H1).
. . .
H1/H3
H2/H4
. . .
Figure 10. HBLK Masking Control
HBLK
SPECIAL H-BLANK PATTERN IS CREATED USING MULTIPLE HBLK TOGGLE POSITIONS.
H1/H3
H2/H4
TOG1
TOG2
TOG3
TOG4
TOG5
TOG6
Figure 11. Generating Special HBLK Patterns
GENERATING SPECIAL HBLK PATTERNS
Six toggle positions are available for HBLK. Normally, only
two of the toggle positions are used to generate the standard
HBLK interval. However, the additional toggle positions may be
used to generate special HBLK patterns, as shown in Figure 11.
The pattern in this example uses all six toggle positions to
generate two extra groups of pulses during the HBLK inter-
val. By changing the toggle positions, different patterns can
be created.
Horizontal Sequence Control
The AD9948 uses sequence change positions (SCPs) and sequence
pointers (SPTRs) to organize the individual horizontal sequences.
Up to four SCPs are available to divide the readout into four
separate regions, as shown in Figure 12. The SCP 0 is always hard-
coded to Line 0, and SCP1–SCP3 are register programmable.
During each region bounded by the SCP, the SPTR registers
designate which sequence is used by each signal. CLPOB, PBLK,
and HBLK each have a separate set of SCPs. For example,
CLPOBSCP1 will define Region 0 for CLPOB, and in that region,
any of the four individual CLPOB sequences may be selected with
the CLPOBSPTR register. The next SCP defines a new region,
and in that region each signal can be assigned to a different
individual sequence. The sequence control registers are sum-
marized in Table XIV.
External HBLK Signal
The AD9948 can also be used with an external HBLK signal. Set-
ting the HBLKDIR register (Address x040) to high will disable the
internal HBLK signal generation. The polarity of the external
signal is specified using the HBLKPOL register, and the mask-
ing polarity of H1 is specified using the HBLKMASK register.
Table XV summarizes the register values when using an external
HBLK signal.
Table XIV. Horizontal Sequence Control Parameters for CLPOB, PBLK, and HBLK
Register
Length
Range
Description
SCP
12b
0–4095 Line Number
CLOB/PBLK/HBLK SCP to Define Horizontal Regions 0–3.
SPTR
2b
0–3 Sequence Number
Sequence Pointer for Horizontal Regions 0–3.
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