參數(shù)資料
型號(hào)： AD9948
廠商： Analog Devices, Inc.
英文描述： 10-Bit CCD Signal Processor with Precision Timing⑩ Core
中文描述： 10位CCD信號(hào)處理器核心精確定時(shí)⑩
文件頁數(shù)： 2/28頁
文件大?。?/td> 539K
代理商： AD9948
REV. 0
–2–
AD9948–SPECIFICATIONS
GENERAL SPECIFICATIONS
DIGITAL SPECIFICATIONS
Parameter
Symbol
Min
Typ
Max
Unit
LOGIC INPUTS
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
Low Level Input Current
Input Capacitance
V
IH
V
IL
I
IH
I
IL
C
IN
2.1
V
V
μ
A
μ
A
pF
0.6
10
10
10
LOGIC OUTPUTS
High Level Output Voltage, I
OH
= 2 mA
Low Level Output Voltage, I
OL
= 2 mA
CLI INPUT
High Level Input Voltage
(TCVDD/2 + 0.5 V)
Low Level Input Voltage
V
OH
V
OL
2.2
V
V
0.5
V
IH–CLI
V
IL–CLI
1.85
V
V
0.85
RG AND H-DRIVER OUTPUTS
High Level Output Voltage
(RGVDD – 0.5 V and HVDD – 0.5 V)
Low Level Output Voltage
Maximum Output Current (Programmable)
Maximum Load Capacitance
V
OH
V
OL
2.2
V
V
mA
pF
0.5
30
100
Specifications subject to change without notice.
Parameter
Min
Typ
Max
Unit
TEMPERATURE RANGE
Operating
Storage
–20
–65
+85
+150
°
C
°
C
MAXIMUM CLOCK RATE
25
MHz
POWER SUPPLY VOLTAGE
AVDD, TCVDD (AFE, Timing Core)
HVDD (H1–H4 Drivers)
RGVDD (RG Driver)
DRVDD (D0–D9 Drivers)
DVDD (All Other Digital)
2.7
2.7
2.7
2.7
2.7
3.0
3.0
3.0
3.0
3.0
3.6
3.6
3.6
3.6
3.6
V
V
V
V
V
POWER DISSIPATION
25 MHz, HVDD = RGVDD = 3 V, 100 pF H1–H4 Loading
*
Total Shutdown Mode
220
1
mW
mW
*
The total power dissipated by the HVDD supply may be approximated using the equation
=
×
(
Reducing the H-loading, using only two of the outputs, and/or using a lower HVDD supply will reduce the power dissipation.
Specifications subject to change without notice.
Total HVDD Power
C
HVDD
Pixel Frequency
HVDD
Number of H
Outputs Used
LOAD
×
×
×
)
(
)
(T
MIN
to T
MAX
, AVDD = DVDD = DRVDD = HVDD = RGVDD = 2.7 V,
C
L
= 20 pF, unless otherwise noted.)
相關(guān)PDF資料
PDF描述
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