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參數(shù)資料
| 型號： | AD9942 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Dual-Channel, 14-Bit CCD Signal Processor with Precision Timing⑩ Core |
| 中文描述： | 雙通道，14位CCD信號處理器核心精確定時⑩ |
| 文件頁數(shù)： | 25/36頁 |
| 文件大?。?/td> | 452K |
| 代理商： | AD9942 |
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AD9942
Table 20. Channel A and Channel B HBLK Individual Sequence Parameters
Length
(Bit)
Range
HBLKMASK
1
High/low
Toggle Position 1
12
0 to 4095 pixel locations
Toggle Position 2
12
0 to 4095 pixel locations
Toggle Position 3
12
0 to 4095 pixel locations
Toggle Position 4
12
0 to 4095 pixel locations
Toggle Position 5
12
0 to 4095 pixel locations
Toggle Position 6
12
0 to 4095 pixel locations
Rev. A | Page 25 of 36
Parameter
Description
Masking polarity for H1 for Sequences 0 to 3 (0 = low; 1 = high).
First toggle position within the line for Sequences 0 to 3.
Second toggle position within the line for Sequences 0 to 3.
Third toggle position within the line for Sequences 0 to 3.
Fourth toggle position within the line for Sequences 0 to 3.
Fifth toggle position within the line for Sequences 0 to 3.
Sixth toggle position within the line for Sequences 0 to 3.
Table 21. Channel A and Channel B Horizontal Sequence Control Registers for CLPOB, PBLK, and HBLK
Length
(Bit)
Range
SCP
12
0 to 4095 line numbers
SPTR
2
0 to 3 sequence numbers
Register
Description
CLPOB/PBLK/HBLK SCP to define Horizontal Regions 0 to 3.
Sequence pointer for Horizontal Regions 0 to 3.
Table 22. Channel A and Channel B External HBLK Register Parameters
Register
Length (Bit)
Range
HBLKDIR
1
High/low
HBLKPOL
1
High/low
HBLKEXTMASK
1
High/low
Description
Specifies HBLK internally generated or externally supplied. 0 = internal; 1 = external.
External HBLK active polarity. 0 = active low; 1 = active high.
External HBLK masking polarity. 0 = mask H1 low; 1 = mask H1 high.
H-COUNTER SYNCHRONIZATION
The H-counter reset occurs seven CLI cycles after the HD falling edge.
0
0
1
2
3
4
5
6
7
8
9
10
11
12
14
15
0
1
2
3
H-COUNTER
RESET
VD_X
NOTES
1. INTERNAL H COUNTER IS RESET SEVEN CLI_X CYCLES AFTER THE HD_X FALLING EDGE (WHEN USING VDHDEDGE = 0).
2. TYPICAL TIMING RELATIONSHIP: CLI_X RISING EDGE IS COINCIDENT WITH HD_X FALLING EDGE.
HD_X
CLI_X
X
X
X
X
X
X
X
H COUNTER
(PIXEL COUNTER)
X
X
X
Figure 26. H-Counter Synchronization
相關(guān)PDF資料 |
PDF描述 |
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| AD9942BBCZ | Dual-Channel, 14-Bit CCD Signal Processor with Precision Timing⑩ Core |
| AD9942BBCZRL | Dual-Channel, 14-Bit CCD Signal Processor with Precision Timing⑩ Core |
| AD9943 | Label Printer Tape RoHS Compliant: NA |
| AD9944 | Complete 10-Bit and 12-Bit, 25 MHz CCD Signal Processors |
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相關(guān)代理商/技術(shù)參數(shù) |
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| AD9942BBCZ | 功能描述:IC PROCESSOR SGNL 14B 100CSPBGA RoHS:是 類別:集成電路 (IC) >> 專用 IC 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1 系列:- 類型:調(diào)幀器 應(yīng)用:數(shù)據(jù)傳輸 安裝類型:表面貼裝 封裝/外殼:400-BBGA 供應(yīng)商設(shè)備封裝:400-PBGA（27x27） 包裝:散裝 |
| AD9942BBCZRL | 功能描述:IC PROCESSOR SGNL 14B 100CSPBGA RoHS:是 類別:集成電路 (IC) >> 專用 IC 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1 系列:- 類型:調(diào)幀器 應(yīng)用:數(shù)據(jù)傳輸 安裝類型:表面貼裝 封裝/外殼:400-BBGA 供應(yīng)商設(shè)備封裝:400-PBGA（27x27） 包裝:散裝 |
| AD9943 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Complete 10-Bit and 12-Bit, 25 MHz CCD Signal Processors |
| AD9943KCP | 制造商:Analog Devices 功能描述:AFE Video 1ADC 10-Bit 3V 32-Pin LFCSP EP 制造商:Rochester Electronics LLC 功能描述:10 BIT 25 MHZ LOW COST ANALOG FRONT END - Bulk |
| AD9943KCPRL | 制造商:Analog Devices 功能描述:AFE Video 1ADC 10-Bit 3V 32-Pin LFCSP EP T/R |
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