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參數(shù)資料
| 型號(hào)： | AD9942 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Dual-Channel, 14-Bit CCD Signal Processor with Precision Timing⑩ Core |
| 中文描述： | 雙通道，14位CCD信號(hào)處理器核心精確定時(shí)⑩ |
| 文件頁數(shù)： | 22/36頁 |
| 文件大?。?/td> | 452K |
| 代理商： | AD9942 |
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AD9942
CHANNEL A AND CHANNEL B HORIZONTAL CLAMPING AND BLANKING
The AD9942 horizontal clamping and blanking pulses are fully
programmable to suit a variety of applications. Individual
sequences are defined for each signal, which are then organized
into multiple regions during image readout. This allows the
dark pixel clamping and blanking patterns to be changed at
each stage of the readout to accommodate different image
transfer timing and high speed line shifts.
Rev. A | Page 22 of 36
INDIVIDUAL CLPOB AND PBLK SEQUENCES
The AFE horizontal timing consists of CLPOB and PBLK, as
shown in Figure 21. These two signals are independently
programmed using the parameters shown in Table 19. The start
polarity, first toggle position, and second toggle position are
fully programmable for each signal. The CLPOB and PBLK
signals are active low and should be programmed accordingly.
Up to four individual sequences can be created for each signal.
INDIVIDUAL HBLK SEQUENCES
The HBLK programmable timing, shown in Figure 22, is similar
to CLPOB and PBLK. However, there is no start polarity
control. Only the toggle positions are used to designate the start
and stop positions of the blanking period. Additionally, there is
a polarity control, HBLKMASK, which designates the polarity
of the horizontal clock signal H1 during the blanking period.
Setting HBLKMASK high sets H1 low and H2 high during the
blanking, as shown in Figure 23. Up to four individual
sequences are available for HBLK.
Table 19. Channel A and Channel B CLPOB and PBLK Individual Sequence Parameters
Length
(Bit)
Range
Polarity
1
High/low
Toggle Position 1
12
0 to 4095 pixel locations
Toggle Position 2
12
0 to 4095 pixel locations
Parameter
Description
Starting polarity of CLPOB and PBLK pulses for Sequences 0 to 3.
First toggle position within the line for Sequences 0 to 3.
Second toggle position within the line for Sequences 0 to 3.
相關(guān)PDF資料 |
PDF描述 |
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| AD9942BBCZ | Dual-Channel, 14-Bit CCD Signal Processor with Precision Timing⑩ Core |
| AD9942BBCZRL | Dual-Channel, 14-Bit CCD Signal Processor with Precision Timing⑩ Core |
| AD9943 | Label Printer Tape RoHS Compliant: NA |
| AD9944 | Complete 10-Bit and 12-Bit, 25 MHz CCD Signal Processors |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
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| AD9942BBCZ | 功能描述:IC PROCESSOR SGNL 14B 100CSPBGA RoHS:是 類別:集成電路 (IC) >> 專用 IC 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1 系列:- 類型:調(diào)幀器 應(yīng)用:數(shù)據(jù)傳輸 安裝類型:表面貼裝 封裝/外殼:400-BBGA 供應(yīng)商設(shè)備封裝:400-PBGA（27x27） 包裝:散裝 |
| AD9942BBCZRL | 功能描述:IC PROCESSOR SGNL 14B 100CSPBGA RoHS:是 類別:集成電路 (IC) >> 專用 IC 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1 系列:- 類型:調(diào)幀器 應(yīng)用:數(shù)據(jù)傳輸 安裝類型:表面貼裝 封裝/外殼:400-BBGA 供應(yīng)商設(shè)備封裝:400-PBGA（27x27） 包裝:散裝 |
| AD9943 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Complete 10-Bit and 12-Bit, 25 MHz CCD Signal Processors |
| AD9943KCP | 制造商:Analog Devices 功能描述:AFE Video 1ADC 10-Bit 3V 32-Pin LFCSP EP 制造商:Rochester Electronics LLC 功能描述:10 BIT 25 MHZ LOW COST ANALOG FRONT END - Bulk |
| AD9943KCPRL | 制造商:Analog Devices 功能描述:AFE Video 1ADC 10-Bit 3V 32-Pin LFCSP EP T/R |
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