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參數(shù)資料
| 型號： | AD9929BBCZ |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 消費家電 |
| 英文描述： | CCD Signal Processor with Precision Timing Generator |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PBGA64 |
| 封裝： | 9 X 9 MM, LEAD FREE, PLASTIC, MO-205-AB, CSBGA-64 |
| 文件頁數(shù)： | 56/64頁 |
| 文件大?。?/td> | 558K |
| 代理商： | AD9929BBCZ |
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AD9929
STANDBY MODE OPERATION
Recommended Standby Mode Sequence
When the AD9929 is going into standby operation, the follow-
ing sequence is recommended (refer to Figure 67 for each step).
Rev. A | Page 56 of 64
1.
Program OUTCONT_REG (Address 0x05) = 0. This
asserts the internal OUTCONT signal low, causing all
digital outputs to become disabled.
2.
Program registers AFESTBY (Address 0x05) = 0 and
DIGSTBY (Address 0x05) = 0. The AD9929 is now in
standby operation.
3.
When ready to come out of standby operation, program
register DIGSTBY (Address 0x05) = 1 and register
AFESTBY (Address 0x05) = 1.
4.
Program necessary control registers.
5.
Program control register MODE (Address 0x0A) = 0. This
selects Mode_A operation.
6.
Program register OUTCONT_REG (Address 0x05) = 1.
This asserts the internal OUTCONT signal high, causing
all digital outputs to become active.
SERIAL
WRITES
VD
(OUTPUT)
DIGITAL
OUTPUTS
H2, RG, MSHUT, STROBE, FD
H1, VSUB
CLI
(INPUT)
HD
(OUTPUT)
OUTCONT
(INTERNAL SIGNAL)
AFESTBY
(REGISTER)
DIGSTBY
(REGISTER)
DCLK1
AND
DCLK2
1
3
1
NOTES
1
DCLK2 WILL BE OUTPUT ON THE FD/DCLK2 PIN 16 PROVIDING REGISTER DCLK2SEL (ADDRESS 0xD5) = 1.
2
IT TAKES 11 CLI CLOCKS FROM WHEN OCONT GOES HIGH UNTIL VD, HD, AND DIGITAL OUTPUT DATA IS VALID.
Figure 67. Recommended Standby Sequence
5
6
2
AD9929
SUPPLIES
0
t
DELAY2
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| AD9929BBCZRL | 制造商:Rochester Electronics LLC 功能描述: 制造商:Analog Devices 功能描述: |
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| AD9937BCPZRL-24 | 制造商:Analog Devices 功能描述: |
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