參數(shù)資料
型號(hào)： AD9927BBCZRL
廠商： ANALOG DEVICES INC
元件分類： 消費(fèi)家電
英文描述： 14-Bit CCD Signal Processor with V-Driver and Precision TimingTM Generator
中文描述： SPECIALTY CONSUMER CIRCUIT, BGA128
封裝： 9 X 9 MM, LEAD FREE, MO-225, CSP_BGA-128
文件頁(yè)數(shù)： 87/100頁(yè)
文件大?。?/td> 784K
代理商： AD9927BBCZRL
AD9927
Rev. 0 | Page 87 of 100
Address
24
25
Data
Bits
[0]
[1]
[2]
[3]
[4]
[5]
[6]
[7]
[8]
[9]
[10]
[11]
[12]
[13]
[14]
[24:0]
Default
Value
0
1
0
0
0
1
0
1
1
1
1
0
0
0
1
0
Update
Type
SCK
SCK
Name
SEL_VCO
SEL_DIV
SEL_CLI
O31V
O32V
O33V
O34V
TEST
TEST
TEST
TEST
TEST
TEST
TEST
CP_PDN
VT_STBY12
Description
1: internal CP clock select VCO.
1: internal CP clock select divided-down version of CLI (default).
1: internal CP clock select CLI.
1: CP output voltage is 3.1 V.
1: CP output voltage is 3.2 V.
1: CP output voltage is 3.3 V.
1: CP output voltage is 3.4 V.
Test use only. Use default values only.
Test use only. Use default values only.
Test use only. Use default values only.
Test use only. Use default values only.
Test use only. Use default values only.
Test use only. Use default values only.
Test use only. Use default values only.
Charge pump power-down. 1: power-down; 0: CP is running.
[23:0] Standby1 and Standby2 polarity for XV[23:0].
[24] Standby1 and Standby2 polarity for XSUBCK.
Settings also apply when OUTCONTROL = low.
[23:0] Standby3 polarity for XV [23:0].
[24] Standby3 polarity for XSUBCK.
Standby1 and Standby2 polarity for GPO [7:0].
Settings also apply when OUTCONTROL = low.
Standby3 polarity for GPO [7:0].
26
[24:0]
0
SCK
VT_STBY3
27
[7:0]
0
SCK
GP_STDBY12
[15:8]
GP_STDBY3
Table 52. Memory Configuration and MODE Registers
Address
Data Bits
28
[4:0]
[9:5]
2A
[2:0]
2B
[4:0]
[9:5]
[14:10]
[19:15]
[24:20]
2C
[4:0]
[9:5]
Default Value
0
0
0
0
0
0
0
0
0
0
Update Type
SCK
SCK
SCK
SCK
Name
VPATNUM
SEQNUM
MODE
FIELD0
FIELD1
FIELD2
FIELD3
FIELD4
FIELD5
FIELD6
Description
Total number of V-pattern groups.
Total number of V-sequences.
Total number of fields in MODE.
Selected first field in MODE.
Selected second field in MODE.
Selected third field in MODE.
Selected fourth field in MODE.
Selected fifth field in MODE.
Selected sixth field in MODE.
Selected seventh field in MODE.
Table 53. Timing Core Registers
Data
Bits
30
[5:0]
[13:8]
[16]
31
[5:0]
[13:8]
[16]
32
[5:0]
[13:8]
[16]
Address
Default
Value
0
20
1
0
20
1
0
20
1
Update
Type
SCK
SCK
SCK
Name
H1POSLOC
H1NEGLOC
H1POL
H2POSLOC
H2NEGLOC
H2POL
HLPOSLOC
HLNEGLOC
HLPOL
Description
H1 rising edge location.
H1 falling edge location.
H1 polarity control. 0: inverse of Figure 20; 1: no inversion.
H2 rising edge location (H5 in HCLK Mode 3).
H2 falling edge location (H5 in HCLK Mode 3).
H2 polarity (H5 in HCLK Mode 3). 0: inverse of Figure 20; 1: no inversion.
HL rising edge location.
HL falling edge location.
HL polarity control. 0: inverse of Figure 20; 1: no inversion.
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