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| 型號： | AD9913BCPZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 29/32頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DDS 10BIT DAC 250MSPS 32LFCSP |
| 產(chǎn)品培訓(xùn)模塊： | Direct Digital Synthesis Tutorial Series (1 of 7): Introduction Direct Digital Synthesizer Tutorial Series (7 of 7): DDS in Action Direct Digital Synthesis Tutorial Series (3 of 7): Angle to Amplitude Converter Direct Digital Synthesis Tutorial Series (6 of 7): SINC Envelope Correction Direct Digital Synthesis Tutorial Series (4 of 7): Digital-to-Analog Converter Direct Digital Synthesis Tutorial Series (2 of 7): The Accumulator |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 分辨率（位）： | 10 b |
| 主 fclk： | 250MHz |
| 調(diào)節(jié)字寬（位）： | 32 b |
| 電源電壓： | 1.8V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 32-VFQFN 裸露焊盤，CSP |
| 供應(yīng)商設(shè)備封裝： | 32-LFCSP-VQ（5x5） |
| 包裝： | 托盤 |
| 產(chǎn)品目錄頁面： | 552 (CN2011-ZH PDF) |
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AD9913
Rev. A | Page 6 of 32
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
PIN 1
INDICATOR
1
PS2/ADR5/D5
NOTES
1. EXPOSED PAD SHOULD BE SOLDERED TO GROUND.
2
PS1/ADR4/D4
3
PS0/ADR3/D3
4
DVDD
5
DGND
6
ADR2/D2
7
ADR1/D1
8
ADR0/D0
24 RSET
23 AGND
22 AVDD
21 AGND
20 IOUT
19 IOUT
18 AGND
17 AVDD
9
S
Y
N
C
_
C
L
K
1
0
S
E
R
/P
A
R
1
A
G
N
D
1
2
A
V
D
1
3
R
E
F
_
C
L
K
1
4
R
E
F
_
C
L
K
1
5
A
G
N
D
1
6
A
V
D
3
2
A
D
R
6
/D
6
3
1
A
D
R
7
/D
7
3
0
S
C
L
K
(P
C
L
K
)
2
9
S
D
IO
(W
R
/R
D
)
2
8
C
S
2
7
IO
_
U
P
D
A
T
E
2
6
P
W
R
_
D
W
N
_
C
T
L
2
5
M
A
S
T
E
R
_
R
E
S
E
T
TOP VIEW
(Not to Scale)
AD9913
07
00
2-
0
03
Figure 3. Pin Configuration
Table 3. Pin Function Descriptions
Pin No.
Mnemonic
I/O
Description
1
PS2/ADR5/D5
I/O
Multipurpose pin: Profile Select Pin (PS2) in Direct Switch Mode, Parallel Port Address Line (ADR5), and
Data Line (D5) to program registers.
2
PS1/ADR4/D4
I/O
Multipurpose pin: Profile Select Pin (PS1) in Direct Switch Mode or Linear Sweeping Mode, Parallel Port
Address Line (ADR4), and Data Line (D4) to program registers.
3
PS0/ADR3/D3
I/O
Multipurpose pin: Profile Select Pin (PS0) in Direct Switch Mode or Linear Sweeping Mode, Parallel Port
Address Line (ADR3), and Data Line (D3) to program registers.
4
DVDD
I
Digital Power Supply (1.8 V).
5
DGND
I
Digital Ground.
6
ADR2/D2
I/O
Parallel Port Address Line 2 and Data Line 2.
7
ADR1/D1
I/O
Parallel Port Address Line 1and Data Line 1.
8
ADR0/D0
I/O
Parallel Port Address Line 0 and Data Line 0.
9
SYNC_CLK
O
Clock Out. The profile pins [PS0:PS2] and the IO_UPDATE pin (Pin 27) should be set up to the rising
edge of this signal to maintain constant pipe line delay through the device.
10
SER/PAR
I
Serial Port and Parallel Port Selection. Logic low = serial mode; logic high = parallel mode.
11, 15,
18, 21,
23
AGND
I
Analog Ground.
12, 16,
17, 22
AVDD
I
Analog Power Supply (1.8 V).
13
REF_CLK
I
Reference Clock Input. See the REF_CLK Overview section for more details.
14
REF_CLK
I
Complementary Reference Clock Input. See the REF_CLK Overview section for more details.
19
IOUT
O
Open Source DAC Complementary Output Source. Current mode. Connect through 50 Ω to AGND.
20
IOUT
O
Open Source DAC Output Source. Current mode. Connect through 50 Ω to AGND.
24
RSET
I
Analog Reference. This pin programs the DAC output full-scale reference current. Attach a 4.64 kΩ
resistor to AGND.
25
MASTER_RESET
I
Master Reset, Digital Input (Active High). This pin clears all memory elements and reprograms registers
to default values.
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