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參數(shù)資料
| 型號： | AD9913BCPZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 17/32頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DDS 10BIT DAC 250MSPS 32LFCSP |
| 產(chǎn)品培訓(xùn)模塊： | Direct Digital Synthesis Tutorial Series (1 of 7): Introduction Direct Digital Synthesizer Tutorial Series (7 of 7): DDS in Action Direct Digital Synthesis Tutorial Series (3 of 7): Angle to Amplitude Converter Direct Digital Synthesis Tutorial Series (6 of 7): SINC Envelope Correction Direct Digital Synthesis Tutorial Series (4 of 7): Digital-to-Analog Converter Direct Digital Synthesis Tutorial Series (2 of 7): The Accumulator |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 分辨率（位）： | 10 b |
| 主 fclk： | 250MHz |
| 調(diào)節(jié)字寬（位）： | 32 b |
| 電源電壓： | 1.8V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 32-VFQFN 裸露焊盤，CSP |
| 供應(yīng)商設(shè)備封裝： | 32-LFCSP-VQ（5x5） |
| 包裝： | 托盤 |
| 產(chǎn)品目錄頁面： | 552 (CN2011-ZH PDF) |
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AD9913
Rev. A | Page 24 of 32
1.
The user supplies the PCLK, CS, R/W, and the parallel
address of the register and using the address pins
(ADR0/D0 through ADR7/D7).
Data Read Operation
A typical read operation follows the steps shown in Figure 33.
1.
The user supplies PCLK, CS, R/W, and the parallel address
of the register using the address pins (ADR0 through
ADR7) for the read operation.
2.
CS, R/W, and the address lines must meet the set up and
hold times relative to the 1st PCLK rising edge.
3.
Data lines must meet the set up and hold times relative to
the 2nd PCLK rising edge.
2.
CS, R/W, and the address lines must meet the setup and
hold times relative to the 1st PCLK rising edge.
4.
CS must meet the set up and hold times relative to the 3rd
PCK rising edge.
3.
The user releases the bus to read.
4.
The AD9913 drives data onto the bus after the second
PCLK rising edge.
5.
The IO_UPDATE is not shown in Figure 34. The
IO_UPDATE transfers the contents from a write sequence
to the active register. See the Register Update (I/O Update)
section.
5.
CS must meet the set up and hold times to the 3rd PCLK
rising edge.
Data Write Operation
Write operations work in a similar fashion as read operations
except that the user drives the bus for both PCLK cycles. A
typical write access follows the steps shown in Figure 34.
PCLK
READ OPERATION
ADDR0
DATA0
DATA1
ADDR1
CS
R/W
ADDR/DATA
0.3ns
tCHD
tCSU
tDVLD
tAHD
tASU
3ns
0.3ns
8ns
3ns
07
00
2-
02
8
Figure 33. Parallel Port Read Timing
PCLK
WRITE OPERATION
ADDR/DATA
CS
R/W
DATA1
ADDR1
DATA0
ADDR0
0.3ns
tCHD
0.3ns
tDHD
3ns
tDSU
3ns
tASU
0.3ns
tAHD
3ns
tCSU
07
00
2-
0
29
Figure 34. Parallel Port Write Timing
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD9913BCPZ1 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Low Power 250 MSPS 10-Bit DAC 1.8 V CMOS Direct Digital Synthesizer |
| AD9913BCPZ-REEL7 | 功能描述:IC DDS 250MSPS 10BIT ADC 32LFCSP RoHS:是 類別:集成電路 (IC) >> 接口 - 直接數(shù)字合成 (DDS) 系列:- 產(chǎn)品變化通告:Product Discontinuance 27/Oct/2011 標(biāo)準(zhǔn)包裝:2,500 系列:- 分辨率（位）:10 b 主 fclk:25MHz 調(diào)節(jié)字寬（位）:32 b 電源電壓:2.97 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:帶卷 (TR) |
| AD9913BCPZ-REEL71 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Low Power 250 MSPS 10-Bit DAC 1.8 V CMOS Direct Digital Synthesizer |
| AD9914 | 制造商:AD 制造商全稱:Analog Devices 功能描述:3.5 GSPS Direct Digital Synthesizer with 12-Bit DAC |
| AD9914/PCBZ | 功能描述:數(shù)據(jù)轉(zhuǎn)換 IC 開發(fā)工具 3.5 GSPS DDS w/Upconverter eval bd. RoHS:否 制造商:Texas Instruments 產(chǎn)品:Demonstration Kits 類型:ADC 工具用于評估:ADS130E08 接口類型:SPI 工作電源電壓:- 6 V to + 6 V |
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