- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄373970 > AD9913BCPZ1 (Analog Devices, Inc.) Low Power 250 MSPS 10-Bit DAC 1.8 V CMOS Direct Digital Synthesizer PDF資料下載
參數(shù)資料
| 型號： | AD9913BCPZ1 |
| 廠商： | Analog Devices, Inc. |
| 元件分類： | XO, clock |
| 英文描述： | Low Power 250 MSPS 10-Bit DAC 1.8 V CMOS Direct Digital Synthesizer |
| 中文描述： | 低功耗250 MSPS的10位DAC 1.8伏CMOS直接數(shù)字頻率合成器 |
| 文件頁數(shù)： | 4/32頁 |
| 文件大小： | 473K |
| 代理商： | AD9913BCPZ1 |
第1頁第2頁第3頁當(dāng)前第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁
AD9913
Parameter
MISCELLANEOUS TIMING CHARACTERISTICS
Wake-Up Time
1
Fast Recovery Mode
Full Sleep Mode
Reset Pulse Width High
DATA LATENCY (PIPELINE DELAY)
Frequency, Phase-to-DAC Output
Frequency-to-DAC Output
Phase-to-DAC Output
Delta Tuning Word-to-DAC Output (Linear Sweep)
CMOS LOGIC INPUTS
Logic 1 Voltage
Logic 0 Voltage
Logic 1 Current
Logic 0 Current
Input Capacitance
CMOS LOGIC OUTPUTS
Logic 1 Voltage
Logic 0 Voltage
POWER SUPPLY CURRENT
DVDD (1.8 V) Pin Current Consumption
DAC_CLK_AVDD (1.8 V)
DAC_AVDD (1.8 V) Pin Current Consumption
PLL_AVDD (1.8 V)
CLK_AVDD (1.8 V) Pin Current Consumption
POWER CONSUMPTION
Single Tone Mode
Modulus Mode
Linear Sweep Mode
Power-Down
Full
Safe
PLL Modes
VCO 1
Differential Input Mode
CMOS Input Mode
Crystal Mode
VCO 2
Differential Input Mode
CMOS Input Mode
Crystal Mode
1
Refer to the Power-Down Features section.
2
SYSCLK cycle refers to the actual clock frequency used on-chip by the DDS. If the reference clock multiplier is used to multiply the external reference clock frequency,
the SYSCLK frequency is the external frequency multiplied by the reference clock multiplication factor. If the reference clock multiplier and divider are not used, the
SYSCLK frequency is the same as the external reference clock frequency.
Rev. 0 | Page 4 of 32
Conditions/Comments
Matched latency enabled
Matched latency disabled
Matched latency disabled
1 mA load
PLL enabled, CMOS input
PLL disabled, differential input
PLL enabled, XTAL input
PLL disabled
PLL disabled
PLL enabled
Min
5
1.2
700
700
1.5
Typ
11
11
10
14
3
50
57
52
Max
1
60
0.4
+700
+700
0.125
46.5
4.7
6.2
1.8
4.3
66.5
70.5
68.5
94.6
98.4
15
44.8
11
7.5
5.4
15
11.5
9.4
Unit
SYSCLK cycles
2
μs
SYSCLK cycles
SYSCLK cycles
SYSCLK cycles
SYSCLK cycles
SYSCLK cycles
V
V
nA
nA
pF
V
V
mA
mA
mA
mA
mA
mW
mW
mW
mW
mW
mW
mW
mW
mW
mW
mW
mW
mW
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AD9913BCPZ-REEL71 | Low Power 250 MSPS 10-Bit DAC 1.8 V CMOS Direct Digital Synthesizer |
| AD9920A | 12-Bit CCD Signal Processor with V-Driver and Precision Timing Generator |
| AD9923A | CCD Signal Processor with V-Driver and Precision Timing⑩ Generator |
| AD9923ABBCZ | CCD Signal Processor with V-Driver and Precision Timing⑩ Generator |
| AD9923ABBCZRL | CCD Signal Processor with V-Driver and Precision Timing⑩ Generator |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD9913BCPZ-REEL7 | 功能描述:IC DDS 250MSPS 10BIT ADC 32LFCSP RoHS:是 類別:集成電路 (IC) >> 接口 - 直接數(shù)字合成 (DDS) 系列:- 產(chǎn)品變化通告:Product Discontinuance 27/Oct/2011 標(biāo)準(zhǔn)包裝:2,500 系列:- 分辨率（位）:10 b 主 fclk:25MHz 調(diào)節(jié)字寬（位）:32 b 電源電壓:2.97 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:帶卷 (TR) |
| AD9913BCPZ-REEL71 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Low Power 250 MSPS 10-Bit DAC 1.8 V CMOS Direct Digital Synthesizer |
| AD9914 | 制造商:AD 制造商全稱:Analog Devices 功能描述:3.5 GSPS Direct Digital Synthesizer with 12-Bit DAC |
| AD9914/PCBZ | 功能描述:數(shù)據(jù)轉(zhuǎn)換 IC 開發(fā)工具 3.5 GSPS DDS w/Upconverter eval bd. RoHS:否 制造商:Texas Instruments 產(chǎn)品:Demonstration Kits 類型:ADC 工具用于評估:ADS130E08 接口類型:SPI 工作電源電壓:- 6 V to + 6 V |
| AD9914BCPZ | 功能描述:數(shù)據(jù)轉(zhuǎn)換 IC - 多種 3.5 GSPS DDS w/Upconverter RoHS:否 制造商:Texas Instruments 轉(zhuǎn)換器數(shù)量:1 分辨率:8 bit 工作電源電壓:2.7 V to 5.5 V 功耗: 工作溫度范圍:- 40 C to + 85 C 封裝 / 箱體:MSOP-10 封裝:Reel |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。