參數(shù)資料
型號(hào): AD9913BCPZ1
廠商: Analog Devices, Inc.
元件分類(lèi): XO, clock
英文描述: Low Power 250 MSPS 10-Bit DAC 1.8 V CMOS Direct Digital Synthesizer
中文描述: 低功耗250 MSPS的10位DAC 1.8伏CMOS直接數(shù)字頻率合成器
文件頁(yè)數(shù): 24/32頁(yè)
文件大?。?/td> 473K
代理商: AD9913BCPZ1
AD9913
Data Read Operation
A typical read operation follows the steps shown in Figure 33.
1.
The user supplies PCLK, CS, R/W, and the parallel address
of the register using the address pins (ADR0 through
ADR7) for the read operation.
2.
CS, R/W, and the address lines must meet the setup and
hold times relative to the 1
st
PCLK rising edge.
3.
The user releases the bus to read.
4.
The AD9913 drives data onto the bus after the second
PCLK rising edge.
5.
CS must meet the set up and hold times to the 3
rd
PCLK
rising edge.
Rev. 0 | Page 24 of 32
Data Write Operation
Write operations work in a similar fashion as read operations
except that the user drives the bus for both PCLK cycles. A
typical write access follows the steps shown in Figure 34.
1.
The user supplies the PCLK, CS, R/W, and the parallel
address of the register and using the address pins
(ADR0/D0 through ADR7/D7).
2.
CS, R/W, and the address lines must meet the set up and
hold times relative to the 1
st
PCLK rising edge.
3.
Data lines must meet the set up and hold times relative to
the 2
nd
PCLK rising edge.
4.
CS must meet the set up and hold times relative to the 3
rd
PCK rising edge.
PCLK
READ OPERATION
ADDR0
DATA0
DATA1
ADDR1
CS
R/W
ADDR/DATA
0.3ns
t
CHD
t
CSU
t
DVLD
t
AHD
t
ASU
3ns
0.3ns
8ns
3ns
0
Figure 33. Parallel Port Read Timing
PCLK
WRITE OPERATION
ADDR/DATA
CS
R/W
DATA1
ADDR1
DATA0
ADDR0
0.3ns
t
CHD
0.3ns
t
DHD
3ns
t
DSU
3ns
t
ASU
0.3ns
t
AHD
3ns
t
CSU
0
Figure 34. Parallel Port Write Timing
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