參數(shù)資料
型號(hào): AD9912A/PCBZ
廠商: Analog Devices Inc
文件頁(yè)數(shù): 8/40頁(yè)
文件大?。?/td> 0K
描述: BOARD EVALUATION FOR AD9912
產(chǎn)品培訓(xùn)模塊: Direct Digital Synthesis Tutorial Series (1 of 7): Introduction
Direct Digital Synthesizer Tutorial Series (7 of 7): DDS in Action
Direct Digital Synthesis Tutorial Series (3 of 7): Angle to Amplitude Converter
Direct Digital Synthesis Tutorial Series (6 of 7): SINC Envelope Correction
Direct Digital Synthesis Tutorial Series (4 of 7): Digital-to-Analog Converter
Direct Digital Synthesis Tutorial Series (2 of 7): The Accumulator
標(biāo)準(zhǔn)包裝: 1
主要目的: 計(jì)時(shí),直接數(shù)字合成(DDS)
嵌入式:
已用 IC / 零件: AD9912
主要屬性: 14 位數(shù)模轉(zhuǎn)換器,48 位調(diào)節(jié)字寬
次要屬性: 1GHz 圖形用戶(hù)界面
已供物品:
AD9912
Rev. F | Page 16 of 40
INPUT/OUTPUT TERMINATION RECOMMENDATIONS
DOWNSTREAM
DEVICE
(HIGH-Z)
AD9912
1.8V
HSTL
OUTPUT
100
06
76
3-
0
27
0.01F
Figure 33. AC-Coupled HSTL Output Driver
DOWNSTREAM
DEVICE
(HIGH-Z)
AD9912
1.8V
HSTL
OUTPUT
50
50
06
76
3-
02
8
AVDD/2
Figure 34. DC-Coupled HSTL Output Driver
AD9912
SELF-BIASING
SYSCLK
INPUT
(CRYSTAL
MODE)
10pF*
06
76
3-
0
29
10pF*
REFER TO CRYSTAL
DATA SHEET.
*
Figure 35. SYSCLK Input, Xtal
AD9912
SELF-BIASING
SYSCLK
INPUT
0.1F
100
06
76
3-
03
0
CLOCK
SOURCE
WITH DIFF.
OUTPUT
Figure 36. SYSCLK Differential Input, Non-Xtal
AD9912
SELF-BIASING
SYSCLK
INPUT
0.01F
06
76
3-
04
9
CLOCK SOURCE
WITH
SINGLE-ENDED
1.8V CMOS
OUTPUT
Figure 37. SYSCLK Single-Ended Input, Non-Xtal
AD9912
SELF-BIASING
FDBK INPUT
0.1F
06
76
3-
05
0
100
(OPTIONAL)
Figure 38. FDBK_IN Input
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