參數(shù)資料
型號(hào): AD9912A/PCBZ
廠商: Analog Devices Inc
文件頁數(shù): 7/40頁
文件大小: 0K
描述: BOARD EVALUATION FOR AD9912
產(chǎn)品培訓(xùn)模塊: Direct Digital Synthesis Tutorial Series (1 of 7): Introduction
Direct Digital Synthesizer Tutorial Series (7 of 7): DDS in Action
Direct Digital Synthesis Tutorial Series (3 of 7): Angle to Amplitude Converter
Direct Digital Synthesis Tutorial Series (6 of 7): SINC Envelope Correction
Direct Digital Synthesis Tutorial Series (4 of 7): Digital-to-Analog Converter
Direct Digital Synthesis Tutorial Series (2 of 7): The Accumulator
標(biāo)準(zhǔn)包裝: 1
主要目的: 計(jì)時(shí),直接數(shù)字合成(DDS)
嵌入式:
已用 IC / 零件: AD9912
主要屬性: 14 位數(shù)模轉(zhuǎn)換器,48 位調(diào)節(jié)字寬
次要屬性: 1GHz 圖形用戶界面
已供物品:
AD9912
Rev. F | Page 15 of 40
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76
3-
0
21
0
200
400
600
800
FREQUENCY (MHz)
650
600
550
500
450
A
M
PL
IT
U
D
E
(mV)
NOM SKEW 25°C, 1.8V SUPPLY
WORST CASE (SLOW SKEW 90°C, 1.7V SUPPLY)
06
76
3-
0
24
0
0.5
1.0
1.5
2.0
2.5
TIME (ns)
0.4
0.6
0.2
0
–0.2
–0.4
–0.6
AM
P
L
IT
UD
E
(
V
)
FREQUENCY = 600MHz
tRISE (20%→80%) = 104ps
tFALL (80%→20%) = 107ps
V p-p = 1.17V DIFF.
DUTY CYCLE = 50%
Figure 27. HSTL Output Driver Single-Ended Peak-to-Peak Amplitude vs.
Toggle Rate (100 Ω Across Differential Pair)
Figure 30. Typical HSTL Output Waveform, Nominal Conditions,
DC-Coupled, Differential Probe Across 100 Ω load
06
76
3-
0
22
0
1020
304
FREQUENCY (MHz)
2.5
2.0
1.5
1.0
0.5
0
AM
P
L
IT
UDE
(
V
)
06
76
3-
0
25
0
20
40
60
80
100
TIME (ns)
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
–0.2
AM
P
L
IT
U
DE
(
V
)
FREQUENCY = 20MHz
tRISE (20%→80%) = 5.5ns
tFALL (80%→20%) = 5.9ns
V p-p = 1.8V
DUTY CYCLE = 53%
0
NOM SKEW 25°C, 1.8V SUPPLY (20pF)
WORST CASE (SLOW SKEW 90°C,
1.7V SUPPLY (20pF))
Figure 31. Typical CMOS Output Driver Waveform (@ 1.8 V),
Nominal Conditions, Estimated Capacitance = 5 pF
Figure 28. CMOS Output Driver Peak-to-Peak Amplitude vs. Toggle Rate
(AVDD3 = 1.8 V) with 20 pF Load
06
76
3-
0
23
0
50
100
150
FREQUENCY (MHz)
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
AM
P
L
IT
UDE
(
V
)
NOM SKEW 25°C, 1.8V SUPPLY (20pF)
WORST CASE (SLOW SKEW 90°C,
3.0V SUPPLY (20pF))
06
76
3-
0
26
0
10
2030
405
TIME (ns)
3.3
2.8
2.3
1.8
1.3
0.8
0.3
–0.2
0
AM
P
L
IT
UD
E
(
V
)
FREQUENCY = 40MHz
tRISE (20%→80%) = 2.25ns
tFALL (80%→20%) = 2.6ns
V p-p = 3.3V
DUTY CYCLE = 52%
Figure 32. CMOS Output Driver Waveform (@ 3.3 V),
Nominal Conditions, Estimated Capacitance = 5 pF
Figure 29. CMOS Output Driver Peak-to-Peak Amplitude vs. Toggle Rate
(AVDD3 = 3.3 V) with 20 pF Load
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