參數(shù)資料
型號(hào)： AD9888KSZ-100
廠商： Analog Devices Inc
文件頁數(shù)： 22/36頁
文件大?。?/td> 0K
描述： IC FLAT PANEL INTERFACE 128-MQFP
標(biāo)準(zhǔn)包裝： 66
應(yīng)用： 圖形卡，VGA 接口
接口： 2 線串口
電源電壓： 3 V ~ 3.6 V
封裝/外殼： 128-BFQFP
供應(yīng)商設(shè)備封裝： 128-MQFP（14x20）
包裝： 托盤
安裝類型： 表面貼裝
Data Sheet
AD9888
Rev. C | Page 29 of 36
Address 0x14[1]—Sync-on-Green Detect
This bit indicates when sync activity is detected on the selected
sync-on-green input pin.
Table 36. Sync-on-Green Detection Status
Sync-on-Green Detect Setting
Function
0
No activity detected
1
Activity detected
The sync processing block diagram (Figure 27) shows where
this function is implemented.
Address 0x14[0]—Detected Coast Polarity Status
This bit reports the status of the coast input polarity detection
circuit and can be used to determine the polarity of the coast
input. The location of the detection circuit is shown in Figure 27.
Table 37. Detected Coast Input Polarity Status
Detected Coast Polarity
Status Setting
Function
0
Coast polarity is negative.
1
Coast polarity is positive.
MODE CONTROL 1
Address 0x15[7]—Channel Mode (DEMUX)
This bit determines whether all pixels are presented to a single
port (Port A) or if pixels are alternately demultiplexed to Port A
and Port B.
Table 38. Output Port Mode Settings
Channel Mode Setting
Function
0
All data goes to Port A.
1 (default)
Pixels are alternately presented to
Port A and Port B.
When DEMUX = 0, Port B outputs are in a high impedance
state. The maximum data rate for single-port mode is 110 MHz.
The timing diagrams in Figure 16 to Figure 18 show the effects
of this option.
Address 0x15[6]—Output Mode
This bit determines whether all pixels are presented to Port A
and Port B simultaneously upon every second DATACK rising
edge or if pixels are alternately presented to Port A and Port B
upon successive DATACK rising edges.
Table 39. Output Mode Settings
Output Mode Setting
Function
0
Data is interleaved.
1 (default)
Data is simultaneous on every
other data clock.
When in single-port mode (DEMUX = 0), this bit is ignored.
When in dual-port mode, the Figure 19 to Figure 24 timing
diagrams show the effects of this option.
Address 0x15[5]—A/B Invert Control (OUTPHASE)
This bit determines whether even pixels or odd pixels go to Port A.
Table 40. A/B Invert Control Settings
A/B Invert Control Setting
First Pixel after HSYNC
0 (default)
Port A
1
Port B
In normal operation (OUTPHASE = 0) when operating in dual-
port output mode (DEMUX = 1), the first sample after the HSYNC
leading edge is presented at Port A. Every subsequent odd sample
goes to Port A. All even samples go to Port B.
When OUTPHASE = 1, these ports are reversed and the first
sample goes to Port B.
When DEMUX = 0, this bit is ignored because data always
comes out of only Port A.
Address 0x15[4]—4:2:2 Output Mode Select
This bit configures the output data in 4:2:2 mode. This mode can
be used to reduce the number of data lines used from 24 to 16
for applications using YUV, YCbCr, or YPbPr graphics signals.
A timing diagram for this mode is shown in Figure 25. Recom-
mended input and output configurations are shown in Table 42.
In 4:2:2 mode, the red and blue channels can be interchanged to
help satisfy board layout or timing requirements, but the green
channel must be configured for Y.
Table 41. 4:2:2 Output Mode Select Settings
4:2:2 Output Mode Select
Setting
Output Mode
0 (default)
4:4:4
1
4:2:2
Table 42. 4:2:2 Input/Output Configuration
Channel
Input Connection
Output Format
Red
V
U/V
Green
Y
Blue
U
High impedance
Address 0x15[3]—Input Mux Control
This bit selects analog inputs from either Channel 0 or
Channel 1.
Table 43. Input Mux Control Settings
Input Mux Control Setting
Channel Selected
0 (default)
Channel 0
1
Channel 1
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