參數(shù)資料
型號： AD9886
廠商： Analog Devices, Inc.
英文描述： Analog Interface for Flat Panel Displays
中文描述： 模擬接口的平板顯示器
文件頁數(shù)： 21/32頁
文件大小： 248K
代理商： AD9886
REV. 0
AD9886
–21–
Table V. Control Register Map (Continued)
Write and
Read or
Read Only
Hex
Address
Default
Value
Register
Name
Bits
Function
12H
W
/R
7:0
0
*******
Active
Interface
Bit 7—AIO: Active Interface Override. If set to Logic 1, the user
can select the active interface via Bit 6. If set to Logic 0, the active
interface is selected via Bit 3 in Register 11H.
Bit 6—AIS: Active Interface Select. Logic 0 selects the analog inter-
face as active. Logic 1 selects the digital interface as active. Note:
The indicated interface will be active only if Bit 7 is set to Logic 1
or if both interfaces are active (Bits 6
or
7
and
4 = Logic 1 in
Register 11H).
Bit 5—Active Hsync Override. If set to Logic 1, the user can select
the Hsync to be used via Bit 4. If set to Logic 0, the active interface
is selected via Bit 2 in Register 11H.
Bit 4—Active Hsync Select. Logic 0 selects Hsync as the active
sync. Logic 1 selects Sync-on-Green as the active sync. Note: The
indicated Hsync will be used only if Bit 5 is set to Logic 1 or if
both syncs are active (Bits 6, 7 = Logic 1 in Register 11H.)
Bit 3—Active Vsync Override. If set to Logic 1, the user can select
the Vsync to be used via Bit 2. If set to Logic 0, the active interface
is selected via Bit 1 in Register 11H.
Bit 2—Active Vsync Select. Logic 0 selects Raw Vsync as the
output Vsync. Logic 1 selects Sync Separated Vsync as the output
Vsync. Note: The indicated Vsync will be used only if Bit 3 is set
to Logic 1.
Bit 1—Coast Select. Logic 0 selects the coast input pin to be used for
the PLL coast. Logic 1 selects Vsync to be used for the PLL coast.
Bit 0—
PWRDN
. Full Chip Power-Down, active low. (Logic 0 =
Full Chip Power-Down, Logic 1 = Normal.)
*
0
******
**
0
*****
***
0
****
****
0
***
*****
0
**
******
0
*
*******
1
13H
W
/R
7:0
00100000
Sync
Separator
Threshold
Sync Separator Threshold—Sets how many pixel clocks the sync
separator will count to before toggling high or low. This should be
set to some number greater than the maximum Hsync or equaliza-
tion pulsewidth.
14H
W
/R
7:0
***
1
****
*****
0
**
******
0
*
Control Bits
Bit 4—Test Bit. (Must be set to 1 for proper operation of chip.)
Bit 2—Scan Enable. (Logic 0 = Not Enabled, Logic 1 = Enabled.)
Bit 1—Coast Polarity Override. (Logic 0 = Polarity determined by
chip, Logic 1 = Polarity set by Bit 6 in Register 0Fh.)
Bit 0– Hsync Polarity Override. (Logic 0 = Polarity determined by
chip, Logic 1 = Polarity set by Bit 7 in Register 0Fh.)
*******
0
15H
W
/R
7:0
Test Register
Reserved for future use.
16H
W
/R
7:0
Test Register
Reserved for future use.
17H
RO
7:0
Test Register
Reserved for future use.
18H
RO
7:0
Test Register
Reserved for future use.
NOTE
1
The AD9886 only updates the PLL divide ratio when the LSBs are written to (Register 02h).
相關(guān)PDF資料
PDF描述
AD9886KS-100 Analog Interface for Flat Panel Displays
AD9886KS-140 Analog Interface for Flat Panel Displays
AD9898 CCD Signal Processor with Precision Timing⑩ Generator
AD9898KCP-20 CCD Signal Processor with Precision Timing⑩ Generator
AD9898KCPRL-20 TVPS00RF-21-41S W/ PC CON
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AD9886/PCB 制造商:AD 制造商全稱:Analog Devices 功能描述:Analog Interface for Flat Panel Displays
AD9886KS-100 制造商:Rochester Electronics LLC 功能描述:- Bulk
AD9886KS-140 制造商:Rochester Electronics LLC 功能描述:A/D INTERFACE FOR FLAT PANEL, 140 MSPS - Bulk 制造商:Analog Devices 功能描述:
AD9887 制造商:AD 制造商全稱:Analog Devices 功能描述:Dual Interface for Flat Panel Displays
AD9887/PCB 制造商:Analog Devices 功能描述:INTRFC DUAL FOR FLAT PNL DISPLAYS 160MQFP - Bulk
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。

采購需求

(若只采購一條型號，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺，查看報價

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺，查看報價

*型號 *數(shù)量 廠商 批號 封裝
添加更多采購

我的聯(lián)系方式

*
*
*