參數(shù)資料
型號(hào)： AD9882KSTZ-140
廠商： Analog Devices Inc
文件頁數(shù)： 22/40頁
文件大?。?/td> 0K
描述： IC INTERFACE/DVI 100MHZ 100LQFP
標(biāo)準(zhǔn)包裝： 1
應(yīng)用： 視頻
接口： 模擬，DVI
電源電壓： 3.15 V ~ 3.45 V
封裝/外殼： 100-LQFP
供應(yīng)商設(shè)備封裝： 100-LQFP（14x14）
包裝： 管件
安裝類型： 表面貼裝
AD9882A
Rev. 0 | Page 29 of 40
Table 23. Active Vsync Override Settings
Override
Result
0
Autodetermines the active Vsync
1
Override; Bit 0 determines the
active Vsync.
The default for this register is 0.
0x10 0
Active Vsync Select
This bit is used to select the active Vsync when the override bit
is set (Bit 1).
Table 24. Active Vsync Select Settings
Select
Result
0
Vsync input
1
Sync separator output
The default for this register is 0.
0x11 7
Clamp Function
This bit enables/disables clamping.
Table 25. Clamp Input Signal Source Settings
Clamp Function
Function
0
Internally generated clamp enabled
1
Clamping disabled
0 enables the clamp timing circuitry controlled by clamp
placement and clamp duration. The clamp position and
duration is counted from the trailing edge of Hsync.
1 disables clamping. The three channels are clamped when the
clamp signal is active.
Power-up default value for clamp function is 0.
0x11 6
Red Clamp Select
A bit that determines whether the red channel is clamped to
ground or to midscale. For RGB video, all three channels are
referenced to ground. For YPbPr, the Y channel is referenced to
ground, but the PbPr channels are referenced to midscale.
Clamping to midscale clamps to Pin 74.
Table 26. Red Clamp Select Settings
Clamp
Function
0
Clamp to ground
1
Clamp to midscale (Pin 74)
The default setting for this register is 0.
0x11 5
Green Clamp Select
This bit determines whether the green channel is clamped to
ground or to midscale.
Table 27. Green Clamp Select Settings
Clamp
Function
0
Clamp to ground
1
Clamp to midscale (Pin 74)
The default setting for this register is 0.
0x11 4
Blue Clamp Select
This bit determines whether the blue channel is clamped to
ground or to midscale.
Table 28. Blue Clamp Select Settings
Clamp
Function
0
Clamp to ground
1
Clamp to midscale (Pin 74)
The default setting for this register is 0.
0x11 3
Coast Select
This bit is used to enable or disable the coast signal. If coast is
enabled, the additional decision of using the Vsync input pin
or the output from the sync separator needs to be made
(Register 0x10, Bits 1, 0). To disable coast, the user must set
Register 0x11, Bit 2 to 1 and Register 0x11, Bit 1 to 1.
Table 29. Coast Enable Settings
Select
Result
0
Coast disabled
1
Internally generated coast signal
The default for this register is 1.
0x11 2
Coast Input Polarity Override
This register is used to override the internal circuitry that
determines the polarity of the coast signal going into the PLL.
When disabling coast, Register 11, Bit 2 must be set to 1 and
Register 0x11, Bit 1 must be set to 1. This register works only
when coast is disabled. It does not work with internal coast.
Table 30. Coast Input Polarity Override Settings
Override Bit
Result
0
Coast polarity determined by chip
1
Coast polarity determined by user
The default for coast polarity override is 0.
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