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參數(shù)資料
型號(hào)： AD9882AKSTZ-100
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 40/40頁(yè)
文件大?。?/td> 0K
描述： IC INTERFACE/DVI 100MHZ 100LQFP
標(biāo)準(zhǔn)包裝： 1
應(yīng)用： 視頻
接口： 模擬，DVI
電源電壓： 3.15 V ~ 3.45 V
封裝/外殼： 100-LQFP
供應(yīng)商設(shè)備封裝： 100-LQFP（14x14）
包裝： 管件
安裝類型： 表面貼裝
AD9882A
Rev. 0 | Page 9 of 40
Table 5. Analog Interface Pin List
Pin Type
Mnemonic
Function
Value
Pin
Number
Analog Video Inputs
RAIN
Analog input for Converter R
0.0 V to 1.0 V
70
GAIN
Analog input for Converter G
0.0 V to 1.0 V
65
BAIN
Analog input for Converter B
0.0 V to 1.0 V
59
External Sync/Clock
HSYNC
Horizontal SYNC input
3.3 V CMOS
79
VSYNC
Vertical SYNC input
3.3 V CMOS
80
SOGIN
Sync-on-green input
0.0 V to 1.0 V
64
Sync Outputs
HSOUT
Hsync output (phase-aligned with DATACK)
3.3 V CMOS
88
VSOUT
Vsync output
3.3 V CMOS
87
SOGOUT
Composite SYNC
3.3 V CMOS
89
Voltage Reference Clamp Voltages
REFBYPASS
Internal reference bypass
1.25 V
73
MIDBYPASS
Internal midscale voltage bypass
74
PLL Filter
FILT
Connection for external filter components for
internal PLL
48
Power Supply
VD
Main power supply
3.15 V to 3.45 V
PVD
PLL power supply (nominally 3.3 V)
3.15 V to 3.45 V
VDD
Output power supply
2.2 V to 3.6 V
GND
Ground
0 V
PIN FUNCTION DETAIL: ANALOG INTERFACE
Inputs
RAIN—Analog Input for Red Channel
GAIN—Analog Input for Green Channel
BAIN—Analog Input for Blue Channel
High impedance inputs that accept the red, green, and blue
channel graphics signals, respectively. For RGB, the three
channels are identical and can be used for any colors, but colors
are assigned for convenient reference.
For proper 4:2:2 formatting in a YPbPr application, the Y must
be connected to the GAIN input, the Pb must be connected to the
BAIN input, and the Pr must be connected to the RAIN input.
They accommodate input signals ranging from 0.5 V to 1.0 V
full scale. Signals should be ac-coupled to these pins to support
clamp operation.
Hsync—Horizontal Sync Input
This input receives a logic signal that establishes the horizontal
timing reference and provides the frequency reference for pixel
clock generation. The logic sense of this pin is controlled by
Serial Register Bit 0x10, Bit 6 (Hsync polarity). Only the leading
edge of Hsync is used by the PLL; the trailing edge is used for
clamp timing. When Hsync polarity = 0, the falling edge of
Hsync is used. When Hsync polarity = 1, the rising edge is
active.
The input includes a Schmitt trigger for noise immunity, with a
nominal input threshold of 1.5 V.
Electrostatic discharge (ESD) protection diodes conduct heavily
if this pin is driven more than 0.5 V above the maximum
tolerance voltage (3.3 V) or more than 0.5 V below ground.
VSYNC—Vertical Sync Input
This is the input for vertical sync.
SOGIN—Sync-on-Green Input
This input is provided to assist with processing signals with
embedded sync, typically on the green channel. The pin is
connected to a high speed comparator with an internally
generated threshold, which is set by the value of Register 0x0F,
Bits 7 to 3.
When connected to an ac-coupled graphics signal with
embedded sync, it produces a noninverting digital output
on SOGOUT.
When not used, this input should be left unconnected. For
more details on this function and how it should be configured,
refer to the Sync-on-Green (SOG) section.
SOGOUT—Sync-on-Green Slicer Output
This pin can be programmed to produce either the output from
the sync-on-green slicer comparator or an unprocessed but
delayed version of the Hsync input. See Figure 20, the sync
processing block diagram, to view how this pin is connected.
Note that the output from this pin is the composite sync
without additional processing from the AD9882A.
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