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參數(shù)資料
| 型號： | AD9877-EB |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Mixed-Signal Front End Set-Top Box, Cable Modem |
| 中文描述： | 混合信號前端機(jī)頂盒，電纜調(diào)制解調(diào)器 |
| 文件頁數(shù)： | 4/36頁 |
| 文件大小： | 1094K |
| 代理商： | AD9877-EB |
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AD9877
SPECIFICATIONS
V
AS
= 3.3 V ± 5%, V
DS
= 3.3 V ± 10%, f
OSCIN
= 27 MHz, f
SYSCLK
= 216 MHz, f
MCLK
= 54 MHz (M = 8 and N = 4). ADC sample frequencies
derived from PLL (f
MCLK
), R
SET
= 4.02 kΩ, maximum fine gain, 75 Ω DAC load.
Table 1.
Rev. B | Page 4 of 36
Parameter
SYSTEM CLOCK DAC SAMPLING, f
SYSCLK
Frequency Range (N = 4)
Frequency Range (N = 3)
OSCIN and XTAL CHARACTERISTICS
Frequency Range
Duty Cycle
Input Impedance
MCLK JITTER
Cycle to Cycle (f
MCLK
derived from PLL)
Tx DAC CHARACTERISTICS
Resolution
Full-Scale Output Current
Gain Error (using internal reference)
Offset Error
Reference Voltage (REFIO Level)
Differential Nonlinearity (DNL)
Integral Nonlinearity (INL)
Output Capacitance
Phase Noise @ 1 kHz Offset, 42 MHz Carrier
Output Voltage Compliance Range
Wideband SFDR
5 MHz Analog Out, I
OUT
= 10 mA
65 MHz Analog Out, I
OUT
= 10 mA
Narrow-Band SFDR (±1 MHz Window)
65 MHz Analog Out, I
OUT
= 10 mA
Tx MODULATOR CHARACTERISTICS
I/Q Offset
Pass-Band Amplitude Ripple (f < f
IQCLK
/8)
Pass-Band Amplitude Ripple (f < f
IQCLK
/4)
Stop-Band Response (f > f
IQCLK
× 3/4)
Tx GAIN CONTROL
Gain Step Size
Gain Step Error
Settling Time, 1% (Full-Scale Step)
8-BIT ADC CHARACTERISTICS
Resolution
Conversion Rate
Pipeline Delay
Offset Matching Between I and Q ADCs
Gain Matching Between I and Q ADCs
Analog Input
Input Voltage Range
Differential Input Impedance
Full Power Bandwidth
Input Referred Noise
Temp
Full
Full
Full
25°C
25°C
25°C
N/A
Full
Full
25°C
25°C
25°C
25°C
25°C
25°C
Full
Full
Full
Full
Full
Full
Full
Full
25°C
25°C
25°C
N/A
Full
N/A
Full
25°C
25°C
25°C
Test
Level
II
II
II
II
III
III
N/A
II
I
I
I
III
III
III
III
II
II
II
II
II
II
II
II
III
III
III
N/A
II
N/A
II
III
III
III
Min
3
35
4
2.5
1.18
0.5
48
48
53
50
Typ
50
100||3
6
12
10
1
±1.0
1.23
±2.5
±8
5
110
55
51
69
55
0.5
0.05
1.8
8
3.5
±8.0
±2.0
1
4||2
90
600
Max
232
177
33
65
20
+2.5
1.28
+1.5
±0.1
±0.5
63
16.5
Unit
MHz
MHz
MHz
%
MΩ||pF
ps rms
Bits
mA
% FS
% FS
V
LSB
LSB
pF
dBc/Hz
V
dBc
dBc
dBc
dB
dB
dB
dB
dB
dB
μs
Bits
MHz
ADC cycles
LSBs
LSBs
Vppd
kΩ||pF
MHz
μV
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