參數(shù)資料
型號(hào)： AD9877-EB
廠商： Analog Devices, Inc.
英文描述： Mixed-Signal Front End Set-Top Box, Cable Modem
中文描述： 混合信號(hào)前端機(jī)頂盒，電纜調(diào)制解調(diào)器
文件頁(yè)數(shù)： 23/36頁(yè)
文件大?。?/td> 1094K
代理商： AD9877-EB
AD9877
When this bit is set default low, the AD9877 serial port is in
MSB-first format. In MSB-first mode, the instruction byte and
data bytes must be written from the MSB to the LSB. In MSB-
first mode, the serial port internal byte address generator
decrements for each byte of the multibyte communication cycle.
Rev. B | Page 23 of 36
When incrementing from 0x1F, the address generator changes
to 0x00. When decrementing from 0x00, the address generator
changes to 0x1F.
NOTES ON SERIAL PORT OPERATION
The AD9877 serial port configuration bits reside in Bit 6 and
Bit 7 of Register 0x00. It is important to note that the
configuration changes immediately upon writing to the last bit
of the register. For multibyte transfers, writing to this register
may occur during the middle of the communication cycle.
Care must be taken to compensate for this new configuration
for the remaining bytes of the current communication cycle.
The same considerations apply to setting the RESET bit in
Register 0x00. All other registers are set to their default values,
but the software reset does not affect the bits in Register 0x00. It
is recommended to use only single-byte transfers when chang-
ing serial port configurations or initiating a software reset.
A write to Bits 1, 2, and 3 of Register 0x00 with the same logic
levels as Bits 7, 6, and 5 (bit pattern: XY1001YX binary) allows
the host processor to reprogram a lost serial port configuration
and to reset the registers to their default values. A second write
to Register 0x00 with RESET bit low and serial port configura-
tion as specified above (XY) reprograms the OSCIN multiplier
setting. A changed f
SYSCLK
frequency is stable after a maximum
of 200 f
MCLK
cycles.
CS
R/W
N1
N0
A4
A3
A2
A1
A0 D7nD6n
D20D10D00
D7nD6n
D20D10D00
SCLK
INSTRUCTION CYCLE
DATA TRANSFER CYCLE
SDIO
SDO
0
Figure 22. Serial Register Interface Timing MSB First
D00D10D20
D6nD7n
SCLK
INSTRUCTION CYCLE
DATA TRANSFER CYCLE
SDIO
SDO
CS
A0
A1
A2
A3
A4
N0
N1 R/W D00D10D20
D6nD7n
0
Figure 23. Serial Register Interface Timing LSB First
0
SCLK
INSTRUCTION BIT 7
INSTRUCTION BIT 6
t
SCLK
t
DH
t
PWL
t
PWH
t
DS
SDIO
CS
t
DS
Figure 24. Timing Diagram for Register Write to AD9877
0
SCLK
SDIO
SDO
CS
DATA BIT N
DATA BIT N – 1
t
DV
Figure 25. Timing Diagram for Register Read from AD9877
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