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參數(shù)資料
| 型號(hào)： | AD9862PCB |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Mixed-Signal Front-End (MxFE⑩) Processor for Broadband Communications |
| 中文描述： | 混合寬帶通信信號(hào)前端（MxFE⑩）處理器 |
| 文件頁(yè)數(shù)： | 25/32頁(yè) |
| 文件大?。?/td> | 617K |
| 代理商： | AD9862PCB |
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REV. 0
AD9860/AD9862
–25–
t
R
1
t
R
3
t
R
2
t
R
1
f
CLKOUT1
Rx DATA TIMING No. 1
f
Rx
= CLKOUT 4
Rx DATA TIMING No. 2
f
Rx
= CLKOUT 2
Rx DATA TIMING No. 3
f
Rx
= CLKOUT
Rx DATA TIMING No. 4
f
Rx
= 2 CLKOUT
Figure 9. Rx Timing Diagram
0: B = A
1: B = A/2
00: C = B
01: C = B/2
10: C = B/4
00: E = D
01: E = 2 D
10: E = 4 D
ADC SAMPLE RATE
(NOT TO EXCEED 64MHz)
DLL OUTPUT RATE
(NOT TO EXCEED 128MHz)
CLKOUT2
INPUT Tx DATA RATE
(SINGLE CHANNEL)
TxDAC UPDATE RATE
SINGLE CHANNEL
(CANNOT EXCEED
DLL OUTPUT RATE)
CLKIN
A
B
D
E
ADC DIV2
DLL MULT
INTERP
00: D = C
01: D = C/2
10: D = C/4
C
CLKOUT2 DIV
Figure 10. Single Tx Timing Block Diagram, Alternative Operation
Table I. Rx Data Timing Table
Table Ia. CLKSEL Set Logic Low
ADC
Div 2
See Figure 8 for
Relative Timing
CLKSEL
Decimate
Multiplex
Timing No. 4
Rx Data = 2
CLKOUT1
CLKOUT1 = 1
2
CLKIN
No Mux
Mux
Not Allowed
Timing No. 3
Rx Data = 2
CLKOUT1
CLKOUT1 = 1
2
CLKIN
No Mux
Timing No. 4
Mux
Rx Data(MUXED) = 2
CLKOUT1
CLKOUT1 = 1
2
CLKIN
Timing No. 3
Rx Data = CLKOUT1
CLKOUT1 = 1
2
CLKIN
No Mux
Timing No. 4
Mux
Rx Data(MUXED) = 2
CLKOUT1
CLOUT1 = 1
2
CLKIN
Timing No. 2
No Mux
Rx Data = 1
2
CLKOUT1
CLOUT1 = 1
2
CLKIN
Timing No. 3
Mux
Rx Data(MUXED) = CLKOUT1
CLKOUT1 = 1
2
CLKIN
Low
Div
No
Div
No
Decimation
No
Decimation
Decimation
Decimation
Table Ib. CLKSEL Set Logic High
ADC
Div 2
See Figure 8 for
Relative Timing
CLKSEL
Decimate
Multiplex
Timing No. 3
Rx Data = CLKOUT1
CLKOUT1 = CLKIN
No Mux
Timing No. 4
Mux
Rx Data(MUXED) = 2
CLKOUT1
CLKOUT1 = CLKIN
Timing No. 2
No Mux
Rx Data = 1
2
CLKOUT1
CLKOUT1 =
CLKIN
Timing No. 3
Mux
Rx Data(MUXED) = CLKOUT1
CLKOUT1 =
CLKIN
Timing No. 2
No Mux
Rx Data = 1
2
CLKOUT1
CLKOUT1 = CLKIN
Timing No. 3
Mux
Rx Data(MUXED) = CLKOUT1
CLOUT1 = CLKIN
Timing No. 1
No Mux
Rx Data = 1
4
CLKOUT1
CLOUT1 = CLKIN
Timing No. 2
Mux
Rx Data(MUXED) = 1
2
CLKOUT1
CLKOUT1 = CLKIN
High
Div
No
Div
No
Decimation
No
Decimation
Decimation
Decimation
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AD9860 | Mixed-Signal Front-End (MxFE⑩) Processor for Broadband Communications |
| AD9860BST | Mixed-Signal Front-End (MxFE⑩) Processor for Broadband Communications |
| AD9860PCB | Mixed-Signal Front-End (MxFE⑩) Processor for Broadband Communications |
| AD9862 | Mixed-Signal Front-End (MxFE⑩) Processor for Broadband Communications |
| AD9862BST | Mixed-Signal Front-End (MxFE⑩) Processor for Broadband Communications |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD9863 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Mixed-Signal Front-End (MxFE⑩) Baseband Transceiver for Broadband Applications |
| AD9863-50EB | 制造商:Analog Devices 功能描述:12 BIT, 50 MSPS MXFE CONVERTER - Bulk |
| AD9863-50EBZ | 制造商:Analog Devices 功能描述:Evaluation Board For Mixed-Signal Front-End Baseband Transceiver For Broadband Applications 制造商:Analog Devices 功能描述:MIXED-SGNL FRONT-END (MXFE) BASEBAND TRNSCVR FOR BROADBAND A - Bulk |
| AD9863BCP-50 | 制造商:Analog Devices 功能描述:Mixed Signal Front End 64-Pin LFCSP EP 制造商:Rochester Electronics LLC 功能描述:12 BIT, 50 MSPS MXFE DUAL CONVERTER - Bulk 制造商:Analog Devices 功能描述:12BIT MIXED SIGNAL CONVERTER 9863 |
| AD9863BCPRL-50 | 制造商:Analog Devices 功能描述:Mixed Signal Front End 64-Pin LFCSP EP T/R |
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