參數(shù)資料
型號: AD9862PCB
廠商: Analog Devices, Inc.
英文描述: Mixed-Signal Front-End (MxFE⑩) Processor for Broadband Communications
中文描述: 混合寬帶通信信號前端(MxFE⑩)處理器
文件頁數(shù): 11/32頁
文件大?。?/td> 617K
代理商: AD9862PCB
REV. 0
AD9860/AD9862
–11–
INPUT FREQUENCY – MHz
0
100
10
1000
T
–60
–65
–70
–75
–80
–85
–90
–50
–55
–95
–100
BUFFERED BYPASS
2V INPUT, 1 GAIN
BUFFERED 2V
INPUT, 1 GAIN
BUFFERED 1V
INPUT, 2 GAIN
BUFFERED BYPASS
1V INPUT, 2 GAIN
TPC 19. Rx THD vs. f
IN
,
F
ADC
= 64 MSPS
INPUT FREQUENCY – MHz
0
S
100
–60
–65
–70
–75
–80
–85
–90
10
1000
–50
–55
–95
–100
BUFFERED BYPASS
1V INPUT, 2 GAIN
BUFFERED BYPASS
2V INPUT, 1 GAIN
BUFFERED 1V
INPUT, 2 GAIN
BUFFERED 2V
INPUT, 1 GAIN
TPC 22. Rx SFDR @ 64 MSPS
INPUT FREQUENCY – MHz
1
R
1
0
–1
–2
–3
–4
–5
–6
10
100
1000
NO BUFF 2V 1
BUFF 1V 2
BUFF 2V 1
TPC 25. Rx Input Attenuation
f
IN
– MHz
0
200
50
T
–75
–80
–85
–90
–70
150
250
100
–65
–60
–55
–50
300
AD9860 LOW POWER
MODE 1, BUFFER
ENABLED,
1V p-p INPUT,
2
RxPGA GAIN
AD9862 LOW POWER
MODE 1, BUFFER
ENABLED
,
1V p-p INPUT,
2
RxPGA GAIN
AD9860 LOW POWER MODE 1,
BUFFER BYPASSED, 2V p-p INPUT,
1
RxPGA GAIN
AD9862 LOW POWER MODE 1,
BUFFER BYPASSED, 2V p-p INPUT,
1
RxPGA GAIN
TPC 20. Rx THD vs. f
IN
,
F
ADC
= 32 MSPS
f
IN
– MHz
0
200
50
S
–75
–80
–85
–90
–70
150
250
100
–65
–60
–55
–50
300
–95
AD9862 LOW POWER MODE 1,
BUFFER BYPASSED, 2V p-p INPUT,
1
RxPGA GAIN
AD9860
LOW POWER
MODE 1,
BUFFER BYPASSED,
2V p-p INPUT,
1
RxPGA GAIN
AD9862 LOW POWER MODE 1,
BUFFER
ENABLED
, 1V p-p
INPUT, 2
RxPGA GAIN
AD9860
LOW POWER MODE 1,
BUFFER ENABLED,
1V p-p INPUT,
2
RxPGA GAIN
TPC 23. Rx SFDR @ 32 MSPS
f
IN
– MHz
0
I
60
250
240
230
220
210
200
190
20
40
80
100
270
260
180
280
TPC 26. Rx Input Buffer
Impedance vs. f
IN
f
IN
– MHz
0
200
50
T
–75
–80
–85
–90
–70
150
250
100
–65
–60
–55
–50
300
AD9860 LOW POWER
MODE 2, BUFFER
ENABLED,
1V p-p INPUT,
2
RxPGA GAIN
AD9860 LOW POWER MODE 2,
BUFFER BYPASSED, 2Vp-p INPUT,
1
RxPGA GAIN
AD9862 LOW POWER MODE 2,
BUFFER BYPASSED, 2V p-p INPUT,
1
RxPGA GAIN
AD9862
LOW POWER
MODE 2,
BUFFER
ENABLED
,
1V p-p INPUT,
2
RxPGA GAIN
TPC 21. Rx THD vs. f
IN
,
F
ADC
= 16 MSPS
f
IN
– MHz
0
200
50
S
–75
–80
–85
–90
–70
150
250
100
–65
–60
–55
–50
300
–95
AD9862 LOW POWER MODE 2,
BUFFER
ENABLED
, 1V p-p INPUT,
2
RxPGA GAIN
AD9860 LOW POWER MODE 2,
BUFFER BYPASSED, 1V p-p
INPUT, 2
RxPGA GAIN
AD9860
LOW POWER MODE 2,
BUFFER ENABLED,
1V p-p INPUT,
2
RxPGA GAIN
AD9862 LOW POWER
MODE 2, BUFFER BYPASSED,
2V p-p INPUT, 1
RxPGA GAIN
TPC 24. Rx SFDR @ 16 MSPS
f
ADC
– MSPS
0
40
10
R
300
200
100
0
400
30
50
20
500
600
700
800
70
NOMINAL
32MSPS LP MODE
16MSPS LP MODE
60
TPC 27. Rx Analog Power
Consumption
相關PDF資料
PDF描述
AD9860 Mixed-Signal Front-End (MxFE⑩) Processor for Broadband Communications
AD9860BST Mixed-Signal Front-End (MxFE⑩) Processor for Broadband Communications
AD9860PCB Mixed-Signal Front-End (MxFE⑩) Processor for Broadband Communications
AD9862 Mixed-Signal Front-End (MxFE⑩) Processor for Broadband Communications
AD9862BST Mixed-Signal Front-End (MxFE⑩) Processor for Broadband Communications
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