- 您現(xiàn)在的位置：買賣IC網 > PDF目錄1894 > AD9845BJSTZRL (Analog Devices Inc)IC CCD SIGNAL PROC 12BIT 48LQFP PDF資料下載
參數(shù)資料
| 型號： | AD9845BJSTZRL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 10/24頁 |
| 文件大小： | 0K |
| 描述： | IC CCD SIGNAL PROC 12BIT 48LQFP |
| 標準包裝： | 2,000 |
| 類型： | CCD 信號處理器，12 位 |
| 輸入類型： | 邏輯 |
| 輸出類型： | 邏輯 |
| 接口： | 3 線串口 |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-LQFP |
| 供應商設備封裝： | 48-LQFP（7x7） |
| 包裝： | 帶卷 (TR) |
REV.
B
–18–
AD9845B
RR
Gb
Gr
BB
CCD: PROGRESSIVE BAYER
LINE0
GAIN0, GAIN1, GAIN0, GAIN1...
RR
Gr
Gb
BB
LINE1
LINE2
GAIN2, GAIN3, GAIN2, GAIN3...
GAIN0, GAIN1, GAIN0, GAIN1...
MOSAIC SEPARATE COLOR
STEERING MODE
Figure 26. CCD Color Filter Example: Progressive Scan
LINE0
GAIN0, GAIN1, GAIN0, GAIN1...
RR
Gr
LINE1
LINE2
GAIN0, GAIN1, GAIN0, GAIN1...
Gb
BB
LINE0
GAIN2, GAIN3, GAIN2, GAIN3...
LINE1
LINE2
GAIN2, GAIN3, GAIN2, GAIN3...
CCD: INTERLACED BAYER
EVEN FIELD
VD SELECTED COLOR
STEERING MODE
ODD FIELD
Gb
BB
Gb
BB
Gb
BB
RR
Gr
RR
Gr
RR
Gr
Figure 27. CCD Color Filter Example: Interlaced
The same Bayer pattern can also be interlaced, and the VD
selected mode should be used with this type of CCD (see
Figure 27). The color steering performs the proper multiplexing
of the R, G, and B gain values (loaded into the PxGA gain regis-
ters) and is synchronized by the user with vertical (VD) and
horizontal (HD) sync pulses. For more detailed information, see
the PxGA Timing section. The PxGA gain for each of the four
channels is variable from –2.5 dB to +9.5 dB, controlled in 64
steps through the serial interface. The PxGA gain curve is
shown in Figure 28.
PxGA GAIN REGISTER CODE
8
32
PxGA
GAIN
–
dB
40
48
58
0
8
16
24
31
6
4
2
0
–2
–4
(011111)
(100000)
10
Figure 28. PxGA Gain Curve
Variable Gain Amplifier
The VGA stage provides a gain range of 2 dB to 36 dB, program-
mable with 10-bit resolution through the serial digital interface.
Combined with approximately 4 dB from the PxGA stage, the
total gain range for the AD9845B is 6 dB to 40 dB. The mini-
mum gain of 6 dB is needed to match a 1 V input signal with
the ADC full-scale range of 2 V. When compared to 1 V full-
scale systems (such as ADI’s AD9803), the equivalent gain
range is 0 dB to 34 dB.
The VGA gain curve follows a “l(fā)inear-in-dB” shape. The exact
VGA gain can be calculated for any gain register value by using
the following equation:
Code Range
Gain Equation (dB)
0–1023
Gain = (0.0353)(Code)
As shown in the CCD Mode Specifications, only the VGA gain
range from 2 dB to 36 dB has tested and guaranteed accuracy.
This corresponds to a VGA gain code range of 77 to 1023. The
Gain Accuracy Specifications also include a PxGA gain of approxi-
mately 3.3 dB, for a total gain range of 6 dB to 40 dB.
VGA GAIN REGISTER CODE
36
0
VGA
GAIN
–
dB
127
255
383
511
639
767
895
1023
30
24
18
12
6
0
Figure 29. VGA Gain Curve (Gain from PxGA Not Included)
Optical Black Clamp
The optical black clamp loop is used to remove residual offsets
in the signal chain and to track low frequency variations in the
CCD’s black level. During the optical black (shielded) pixel
interval on each line, the ADC output is compared with a fixed
black level reference selected by the user in the clamp level
register. The clamp level is adjustable from 0 to 255 LSB, in
256 steps. The resulting error signal is filtered to reduce noise,
and the correction value is applied to the ADC input through a
D/A converter. Normally, the optical black clamp loop is turned
on once per horizontal line, but this loop can be updated more
slowly to suit a particular application. If external digital clamping
is used during the postprocessing, the AD9845B optical black
clamping may be disabled using Bit D5 in the Operation Register
(see the Serial Interface Timing and Internal Register Descrip-
tion section). When the loop is disabled, the clamp level register
may still be used to provide programmable offset adjustment.
Horizontal timing is shown in Figure 6. The CLPOB pulse
should be placed during the CCD’s optical black pixels. It is
recommended that the CLPOB pulse duration be at least
20 pixels wide to minimize clamp noise. Shorter pulsewidths may
相關PDF資料 |
PDF描述 |
|---|---|
| AD9846AJSTZRL | IC CCD SIGNAL PROC 10BIT 48LQFP |
| AD9847AKSTZRL | IC CCD SIGNAL PROC 10BIT 48-LQFP |
| AD9849AKSTZRL | IC CCD SIGNAL PROC 12BIT 48LQFP |
| AD9850BRS | IC DDS DAC W/COMP 125MHZ 28-SSOP |
| AD9851BRS | IC DDS DAC W/COMP 180MHZ 28-SSOP |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| AD9846A | 制造商:AD 制造商全稱:Analog Devices 功能描述:Complete 10-Bit 30 MSPS CCD Signal Processor |
| AD9846AJST | 制造商:Analog Devices 功能描述:AFE VID 1ADC 10-BIT 3.3V 48LQFP - Bulk 制造商:Rochester Electronics LLC 功能描述:10 BIT 30 MSPS CCD SIGNAL PROCESSOR - Tape and Reel |
| AD9846AJSTRL | 制造商:Analog Devices 功能描述:AFE VID 1ADC 10-BIT 3.3V 48LQFP - Tape and Reel 制造商:Rochester Electronics LLC 功能描述:10 BIT 30 MSPS CCD SIGNAL PROCESSOR - Tape and Reel |
| AD9846AJSTZ | 功能描述:IC CCD SIGNAL PROC 10BIT 48LQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 傳感器和探測器接口 系列:- 其它有關文件:Automotive Product Guide 產品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:74 系列:- 類型:觸控式傳感器 輸入類型:數(shù)字 輸出類型:數(shù)字 接口:JTAG，串行 電流 - 電源:100µA 安裝類型:表面貼裝 封裝/外殼:20-TSSOP（0.173"，4.40mm 寬） 供應商設備封裝:20-TSSOP 包裝:管件 |
| AD9846AJSTZRL | 功能描述:IC CCD SIGNAL PROC 10BIT 48LQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 傳感器和探測器接口 系列:- 其它有關文件:Automotive Product Guide 產品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:74 系列:- 類型:觸控式傳感器 輸入類型:數(shù)字 輸出類型:數(shù)字 接口:JTAG，串行 電流 - 電源:100µA 安裝類型:表面貼裝 封裝/外殼:20-TSSOP（0.173"，4.40mm 寬） 供應商設備封裝:20-TSSOP 包裝:管件 |
發(fā)布緊急采購，3分鐘左右您將得到回復。