參數(shù)資料
型號： AD9824KCP
廠商： ANALOG DEVICES INC
元件分類： 模擬信號調(diào)理
英文描述： Complete 14-Bit 30 MSPS CCD Signal Processor
中文描述： SPECIALTY ANALOG CIRCUIT, QCC48
封裝： 7 X 7 MM, LFCSP-48
文件頁數(shù)： 5/24頁
文件大?。?/td> 438K
代理商： AD9824KCP
REV. 0
AD9824
–5–
ABSOLUTE MAXIMUM RATINGS
With
Respect
To
Parameter
Min Max
Unit
AVDD1, AVDD2
DVDD1, DVDD2
DRVDD
Digital Outputs
SHP, SHD, DATACLK
CLPOB, CLPDM, PBLK
SCK, SL, SDATA
VRT, VRB, CMLEVEL
BYP1-3, CCDIN
Junction Temperature
Lead Temperature (10 sec)
AVSS
DVSS
DRVSS
DRVSS
DVSS
DVSS
DVSS
AVSS
AVSS
–0.3 +3.9
–0.3 +3.9
–0.3 +3.9
–0.3 DRVDD + 0.3 V
–0.3 DVDD + 0.3
–0.3 DVDD + 0.3
–0.3 DVDD + 0.3
–0.3 AVDD + 0.3
–0.3 AVDD + 0.3
150
300
V
V
V
V
V
V
V
V
°
C
°
C
TIMING SPECIFICATIONS
Parameter
Symbol
Min
Typ
Max
Unit
SAMPLE CLOCKS
DATACLK, SHP, SHD Clock Period
DATACLK High/Low Pulsewidth
SHP Pulsewidth
SHD Pulsewidth
CLPDM Pulsewidth
CLPOB Pulsewidth
*
SHP Rising Edge to SHD Falling Edge
SHP Rising Edge to SHD Rising Edge
Internal Clock Delay
Inhibited Clock Period
t
CP
t
ADC
t
SHP
t
SHD
t
CDM
t
COB
t
S1
t
S2
t
ID
t
INH
33
13
5
5
4
2
0
15
33
16.7
8.3
8.3
10
20
8.3
16.7
3.0
ns
ns
ns
ns
Pixels
Pixels
ns
ns
ns
ns
10
DATA OUTPUTS
Output Delay
Output Hold Time
Pipeline Delay
t
OD
t
H
13
7.6
9
16
ns
ns
Cycles
7.0
SERIAL INTERFACE
Maximum SCK Frequency
SL to SCK Setup Time
SCK to SL Hold Time
SDATA Valid to SCK Rising Edge Setup
SCK Falling Edge to SDATA Valid Hold
SCK Falling Edge to SDATA Valid Read
f
SCLK
t
LS
t
LH
t
DS
t
DH
t
DV
10
10
10
10
10
10
MHz
ns
ns
ns
ns
ns
*
Minimum CLPOB pulsewidth is for functional operation only. Wider typical pulses are recommended to achieve low noise clamp performance.
Specifications subject to change without notice.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD9824 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
(C
L
= 20 pF, f
SAMP
= 30 MHz, CCD-Mode Timing in Figures 5 and 6, AUX-Mode Timing in Figure 7,
Serial Timing in Figures 21–24.)
ORDERING GUIDE
Temperature
Range
–20
°
C to +85
°
C
Package
Description
Package
Option
Model
AD9824KCP
LFCSP
CP-48
THERMAL CHARACTERISTICS
Thermal Resistance
48-Lead LFCSP Package
θ
JA
= 26
°
C/W
*
*
θ
JA
is measured using a 4-layer PCB with the exposed paddle
soldered to the board.
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