
REV. 0
AD9824
–15–
SDATA
SCK
SL
A0 A1
A2
D0
D10 D0
D9
D0
D0
D7
RNW
0
0
D9
0
0
0
D0
1
2
17
35
34
27
26
16
6
5
4
3
44
45
51
63
62
57
56
50
68
...
...
...
...
...
...
...
...
10 BITS
ACG GAIN
D5
D0
D5
D0
D0
D5
D5
...
...
...
...
...
...
...
...
...
NOTES
1. ANY NUMBER OF ADJACENT REGISTERS MAY BE LOADED SEQUENTIALLY, BEGINNING WITH THE LOWEST ADDRESS AND INCREMENTING ONE ADDRESS AT A TIME.
2. WHEN SEQUENTIALLY LOADING MULTIPLE REGISTERS, THE EXACT REGISTER LENGTH (SHOWN ABOVE) MUST BE USED FOR EACH REGISTER.
3. ALL LOADED REGISTERS WILL BE SIMULTANEOUSLY UPDATED WITH THE RISING EDGE OF SL.
8 BITS
CLAMP LEVEL
10 BITS
CONTROL
11 BITS
OPERATION
6 BITS
PxGA
GAIN0
6 BITS
PxGA
GAIN1
6 BITS
PxGA
GAIN2
6 BITS
PxGA
GAIN3
Figure 23. Continuous Serial Write Operation to All Registers
SDATA
A0
A1
A2
D1
D0
D1
D2
D3
D4
D5
D0
D3
D2
D4
0
0
23
24
1
2
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
29
18
...
...
D5
0
0
1
D5
D5
D0
D0
RNW
SCK
SL
PxGA
GAIN0
PxGA
GAIN1
PxGA
GAIN3
PxGA
GAIN2
...
...
...
Figure 24. Continuous Serial Write Operation to All PxGA Gain Registers
Table II. Operation Register Contents (Default Value x000)
Optical Black Clamp
D5
Reset
D4
Power-Down Modes
D3 D2
Channel Selection
D1 D0
D10
D9
D8
D7
D6
0
1
0
1
0
1
1
2
0
1
0
1
Enable Clamping
Disable
Clamping
0 Normal
1 Reset All Registers
to Default
0
0
1
1
0 Normal Power
1 Test Only
0 Standby
1 Total Power-Down
0
0
1
1
0
1
0
1
CCD Mode
AUX1 Mode
AUX2 Mode
Test Only
NOTES
1
Must be set to zero.
2
Set to one.
Table III. VGA Gain Register Contents (Default Value x000)
MSB
D9
LSB
D0
D10
D8
D7
D6
D5
D4
D3
D2
D1
Gain (dB)
X
0
0
0
1
0
1
1
1
1
1
1
1
2.0
35.965
36.0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1