參數(shù)資料
型號(hào)： AD9821KST
廠商： ANALOG DEVICES INC
元件分類： ADC
英文描述： Complete 12-Bit 40 MSPS Imaging Signal Processor
中文描述： 1-CH 12-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQFP48
封裝： 1.40 MM, PLASTIC, MS-026BBC, LQFP-48
文件頁(yè)數(shù)： 5/16頁(yè)
文件大?。?/td> 277K
代理商： AD9821KST
REV. 0
AD9821
–5–
PIN CONFIGURATION
36
35
34
33
32
31
30
29
28
27
26
25
13 14 15 16 17 18 19 20 21 22 23 24
1
2
3
4
5
6
7
8
9
10
11
12
48 47 46 45 44
39 38 37
43 42 41 40
PIN 1
TOP VIEW
(Not to Scale)
TEST
AVSS
TEST
AVDD2
BYP1
VIN–
VIN+
TEST
TEST
AVDD1
AVSS
AVSS
(LSB) D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
NC = NO CONNECT
AD9821
(MSB) D11
N
N
S
S
S
S
N
D
D
V
V
N
D
D
D
D
D
N
P
C
T
T
T
N
PIN FUNCTION DESCRIPTIONS
Pin Number
1–12
13
14
15, 41
16
17
18, 24, 37, 42, 47, 48
19
20
21–23
25, 26, 35
27
28, 29
30
31
32
33
34, 36
38
39
40
43
44
45
46
Mnemonic
D0–D11
DRVDD
DRVSS
DVSS
DATACLK
DVDD1
NC
PBLK
CLPOB
TEST
AVSS
AVDD1
TEST
VIN+
VIN–
BYP1
AVDD2
TEST
VRT
VRB
DVDD2
STBY
SL
SDATA
SCK
Type
DO
P
P
P
DI
P
NC
DI
DI
DI
P
P
AO
AI
AI
AO
P
AI
AO
AO
P
DI
DI
DI
DI
Description
Digital Data Outputs
Digital Output Driver Supply
Digital Output Driver Ground
Digital Ground
Digital Data Output Latch Clock
Digital Supply
Internally Not Connected. May be Tied High or Low.
Preblanking Clock Input
Black Level Clamp Clock Input
Test Use Only. Tie to VDD or VSS.
Analog Ground
Analog Supply
Test Use Only. Tie to VDD or VSS.
Positive Analog Input for Imager Signal
Negative Analog Input for Imager Signal
Internal Bias Level Decoupling
Analog Supply
Test Use Only. Tie to VDD or VSS.
ADC Top Reference Voltage Decoupling
ADC Bottom Reference Voltage Decoupling
Digital Supply
Standby Mode, Active High. Same as Total Power-Down Mode.
Serial Digital Interface Load Pulse
Serial Digital Interface Data
Serial Digital Interface Clock
TYPE: AI = Analog Input, AO = Analog Output, DI = Digital Input, DO = Digital Output, P = Power.
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