參數(shù)資料
型號: AD9821KST
廠商: ANALOG DEVICES INC
元件分類: ADC
英文描述: Complete 12-Bit 40 MSPS Imaging Signal Processor
中文描述: 1-CH 12-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQFP48
封裝: 1.40 MM, PLASTIC, MS-026BBC, LQFP-48
文件頁數(shù): 14/16頁
文件大小: 277K
代理商: AD9821KST
REV. 0
–14–
AD9821
Internal Power-On Reset Circuitry
After power-on, the AD9821 will automatically reset all internal
registers and perform internal calibration procedures. This takes
approximately 1 ms to complete. During this time, normal clock
signals and serial write operations may occur. However, serial
register writes will be ignored until the internal reset operation
is completed.
Grounding and Decoupling Recommendations
As shown in Figure 13, a single ground plane is recommended
for the AD9821. This ground plane should be as continuous as
possible, particularly around Pins 25 through 39. This will ensure
that all analog decoupling capacitors provide the lowest possible
impedance path between the power and bypass pins and their
respective ground pins. All decoupling capacitors should be
located as close as possible to the package pins. A single clean
power supply is recommended for the AD9821, but a separate
digital driver supply may be used for DRVDD (Pin 13). DRVDD
should always be decoupled to DRVSS (Pin 14), which should
be connected to the analog ground plane. Advantages of using a
separate digital driver supply include using a lower voltage (2.7 V)
to match levels with a 2.7 V ASIC, reducing digital power
dissipation, and reducing potential noise coupling. If the
digital outputs (Pins 1–12) must drive a load larger than 20 pF,
buffering is recommended to reduce digital code transition noise.
Alternatively, placing series resistors close to the digital output
pins may also help reduce noise.
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