
REV. 0
–3–
AD9806
CCD-MODE SPECIFICATIONS
Parameter
Min
Typ
Max
Unit
POWER CONSUMPTION
VDD = 2.7
65
mW
VDD = 3.0
75
mW
VDD = 3.3
85
mW
MAXIMUM CLOCK RATE
18
MHz
CDS
Gain
0dB
Allowable CCD Reset Transient
1
500
mV
Max Input Range before Saturation
1
1000
mV p-p
PGA
Gain Control Resolution
10
Bits
Gain Range (See Figure 5a for Gain Curve)
Low Gain (Code 95)
2
–1
0
+1
dB
Max Gain (1023)
2
32
33
34
dB
BLACK LEVEL CLAMP
Clamp Level (Selected through Serial Interface E-Reg)
CLP0 (E-Reg 00)
32
LSB
CLP1 (E-Reg 01)
48
LSB
CLP2 (E-Reg 10)
64
LSB
CLP3 (E-Reg 11)
16
LSB
SIGNAL-TO-NOISE RATIO
3 (@ Low PGA Gain)
74
dB
TIMING SPECIFICATIONS
4
Pipeline Delay
9
Cycles
Internal Clock Delay
5 (t
ID)3
ns
Inhibited Clock Period (tINHIBIT)10
ns
Output Delay (tOD)14.5
16
ns
Output Hold Time (tHOLD)6
ns
ADCCLK, SHP, SHD Clock Period
47
55.6
ns
ADCCLK High-Level/Low-Level
20
28
ns
SHP, SHD Minimum Pulsewidth
10
14
ns
SHP Rising Edge to SHD Rising Edge
20
28
ns
NOTES
1Input signal characteristics defined as follows:
1V MAX
INPUT
SIGNAL RANGE
200mV MAX
OPTICAL
BLACK PIXEL
500mV TYP
RESET
TRANSIENT
2Use equations on page 8 to calculate gain.
3SNR = 20 log
10 (Full-Scale Voltage/RMS Output Noise).
420 pF loading; timing shown in Figure 1.
5Internal aperture delay for actual sampling edge.
Specifications subject to change without notice.
(TMIN to TMAX, AVDD = DVDD = 3.0 V, fADCCLK = fSHP = fSHD = 18 MHz, unless otherwise noted.)