參數(shù)資料
型號(hào)： AD9786BSVZRL
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 24/56頁(yè)
文件大?。?/td> 0K
描述： IC DAC 16BIT INTERPOL/SP 80TQFP
產(chǎn)品培訓(xùn)模塊： Data Converter Fundamentals
DAC Architectures
標(biāo)準(zhǔn)包裝： 1,000
系列： TxDAC+®
位數(shù)： 16
數(shù)據(jù)接口： 并聯(lián)
轉(zhuǎn)換器數(shù)目： 1
電壓電源： 單電源
功率耗散（最大）： 1.25W
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 80-TQFP 裸露焊盤
供應(yīng)商設(shè)備封裝： 80-TQFP-EP（12x12）
包裝： 帶卷 (TR)
輸出數(shù)目和類型： 2 電流，單極
采樣率（每秒）： 500M
AD9786
Rev. B | Page 30 of 56
Note that the data in Figure 44 to Figure 53 was taken with the
DATAADJ default of 0000. Changing the DATAADJ values allows
the user to select the specific edge of DACCLK upon which the
input data is latched. This can be done in master mode, but it
is most useful in slave mode. For more information on using
DATAADJ and MODADJ to synchronize multiple AD9786s,
see Analog Devices Application Note 747. Table 27 lists the values
available for 8× interpolation, which, in turn, provides a choice of
16 edges to sync data. With 4× interpolation, there is
a choice of eight edges, and the relevant values from Table 27
are 0000, 0010, 0100, 0110, 1000, 1010, 1100, and 1110. These
options allow latching edge placement from +3 cycles to 4 cycles.
In 2× interpolation, four edges are available, and the relevant
values from Table 27 are 0000, 0100, 1000, and 1100. The
choices for DATAADJ are diminished to +1 cycle to –2 cycles.
Figure 54, Figure 55, and Figure 56 show the alignment for the
latching edge of DACCLK with 4× interpolation and different
settings for DATAADJ. In Figure 54, the AD9786 is in
DATACLK master mode. DATAADJ is set to 0000, with
DCLKPOL set to 0 so that the latching edge of DACCLK is
immediately before the rising edge of DATACLK. The data
transitions shown in Figure 54 are synchronous with the
DACCLK, so that DACCLK and input data are constant with
respect to each other.
The only visible change when DATAADJ is altered is that
DATACLK moves, indicating the latching edge has moved as
well. Note that in DATACLK master mode, when DATAADJ is
altered, the latching edge with respect to DATACLK remains
the same.
03152-054
RISING EDGE OF DATACLK
CONCURRENT WITH
LATCHING EDGE OF DACCLK
DATA TRANSITION
DACCLK
LATCHING EDGE
Figure 54. DATAADJ = 0000
Figure 55 shows the same conditions, but with DATAADJ set to
1111. This moves DATACLK to the left in the plot, indicating that
it occurs one DACCLK cycle before it did in Figure 54; therefore,
the latching edge of DACCLK also occurs one cycle earlier.
03152-055
RISING EDGE OF DATACLK
CONCURRENT WITH
LATCHING EDGE OF DACCLK
DATA TRANSITION
DACCLK
LATCHING EDGE
Figure 55. DATAADJ = 1111
Figure 56 shows the same conditions, with DATAADJ set
to 0001; therefore, DATACLK moves to the right in the plot.
This indicates that it occurs one DACCLK cycle after it did in
Figure 54; therefore, the latching edge of DACCLK also occurs
one cycle later.
03152-056
RISING EDGE OF DATACLK
CONCURRENT WITH
LATCHING EDGE OF DACCLK
DATA TRANSITION
DACCLK
LATCHING EDGE
Figure 56. DATAADJ = 0001
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