參數(shù)資料
型號： AD9786BSVRL
廠商： ANALOG DEVICES INC
元件分類： DAC
英文描述： 16-Bit, 200 MSPS/500 MSPS TxDAC+ with 2】/4】/8】 Interpolation and Signal Processing
中文描述： PARALLEL, WORD INPUT LOADING, 16-BIT DAC, PQFP80
封裝： PLASTIC, MS-026-ADD, TQFP-80
文件頁數(shù)： 43/60頁
文件大?。?/td> 1497K
代理商： AD9786BSVRL
AD9786
Master/Slave, Modulator/DATACLK Master Modes
In applications where two or more AD9786s are used to syn-
thesize several digital data paths, it may be necessary to ensure
that the digital inputs to each device are latched synchronously.
In complex data processing applications, digital modulator
phase alignment may be required between two AD9786s. In
order to allow data synchronization and phase alignment, only
one AD9786 should be configured as a master device, providing
a reference clock for another slave-configured AD9786.
Rev. 0 | Page 43 of 60
With synchronization enabled, a reference clock signal is
generated on the DATACLK pin of the master. The DATACLK
pins on the slave devices act as inputs for the reference clock
generated by the master. The DATACLK pin on the master and
all slaves must be directly connected. All master and slave
devices must have the same clock source connected to their
respective CLK+/CLK– pins.
When configured as a master, the reference clock generated may
take one of two forms. In modulator master mode, the reference
clock will be a square wave with a period equal to 16 cycles of
the DAC update clock. Internal to the AD9786 is a 16-state
finite state machine, running at the DAC update rate. This state
machine generates all internal and external synchronization
clocks and modulator phasings. The rising edge of the master
reference clock is time aligned to the internal state machine’s
state zero. Slave devices use the master’s reference clock to
synchronize their data latching and align their modulator’s
phase by aligning their local state machine state zero to the
master.
The second master mode, DATACLK master mode, generates a
reference clock that is at the channel data rate. In this mode, the
slave devices align their internal channel data rate clock to the
master. If modulator phase alignment is needed, a concurrent
serial write to all slave devices is necessary. To achieve this, the
CSB pin on all slaves must be connected together and a group
serial write to the MODADJ register bits must be performed;
the modulator coefficient alignment is updated on the next
rising edge of the internal state machine following a successful
serial write, see Figure 81. Modulator master mode does not
need a concurrent serial write as slaves lock to the master phase
automatically.
In a slave device, the local channel data rate clock and the digital
modulator clock are created from the internal state machine.
The local channel data rate clock is used by the slave to latch
digital input data. At high data rates, the delay inherent in the
signal path from master to slave may cause the slave to lag the
master when acquiring synchronization. To account for this, an
integer number of the DAC update clock cycles may be
programmed into the slave device as an offset. The value in
DATADJ allows the local channel data rate clock in the slave
device to advance by up to eight cycles of the DAC clock or to
be delayed by up to seven cycles, see Figure 84.
The digital modulator coefficients are updated at the DAC clock
rate and decoded in sequential order from the state machine
according to Figure 83. The MODADJ bits can be used to align
a different coefficient to the finite state machine’s zero state as
shown in Figure 84.
DAC
CLOCK
STATE
MACHINE
STATE MACHINE
CYCLE CLOCK
CHANNEL DATA
RATE CLOCK
MODULATOR
COEFFICIENT
MODADJ
000
000
1
0
–1
0
1
0
–1
0
1
0
–1
0
1
0
–1
0
–1
0
1
0
–1
0
1
0
–1
0
1
0
–1
0
1
0
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
0
Figure 81. Synchronous Serial Modulator Phase Alignment
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