參數(shù)資料
型號： AD9786BSVRL
廠商： ANALOG DEVICES INC
元件分類： DAC
英文描述： 16-Bit, 200 MSPS/500 MSPS TxDAC+ with 2】/4】/8】 Interpolation and Signal Processing
中文描述： PARALLEL, WORD INPUT LOADING, 16-BIT DAC, PQFP80
封裝： PLASTIC, MS-026-ADD, TQFP-80
文件頁數(shù)： 29/60頁
文件大小： 1497K
代理商： AD9786BSVRL
AD9786
AD9786 Low Setup/Hold Mode (DATACLK input, data
recovery off)
Rev. 0 | Page 29 of 60
Some applications may require that digital input data be
synchronized with the DATACLK input, rather than DACCLK.
For these applications, the AD9786 can be programmed for Low
Setup/Hold Mode by entering the values in Table 26 into the
SPI registers. With data recovery off and the MODSYNC bit set
to logic 1, the AD9786 will latch data in on the rising or falling
edge of DATACLK input, depending on the state of DCLKPOL.
The timing is similar to the slave mode with data recovery on.
There is still a required timing relationship between DACCLK
and DATACLK in, as shown in Figure 51 and Figure 52. As
these show, the digital input data is latched in on the
DATACLK edge, rather than DACCLK. One advantage of this
mode is that the setup and hold numbers for the input data with
respect to DATACLK are much smaller than the similar specs in
the slave/clock recovery mode.
Note that in this mode, the DATAADJ bits have no effect.
0
t
HT
= 0.0ns MIN
t
S
= –1.1ns MIN
t
H
= 2.8ns MIN
DACCLK
IN
DATACLK
IN
DATA
t
ST
= 3.0ns MIN
Figure 51. Low Setup and Hold Mode Timing, 2× Interpolation, DCLKPOL = 0
0
DACCLK
IN
DATACLK
IN
DATA
t
S
= –1.8ns MIN
t
H
= 3.1ns MIN
t
HT
= 1.0ns MIN
t
ST
= 2.0ns MIN
Figure 52. Low Setup and Hold Mode Timing, 2× Interpolation, DCLKPOL = 1
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