- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄8882 > AD9785BSVZ (Analog Devices Inc)IC DAC 12BIT 800MSPS 100TQFP PDF資料下載
參數(shù)資料
| 型號(hào)： | AD9785BSVZ |
| 廠商： | Analog Devices Inc |
| 文件頁(yè)數(shù)： | 21/64頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC DAC 12BIT 800MSPS 100TQFP |
| 產(chǎn)品培訓(xùn)模塊： | Data Converter Fundamentals DAC Architectures |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | TxDAC® |
| 位數(shù)： | 12 |
| 數(shù)據(jù)接口： | 串行 |
| 轉(zhuǎn)換器數(shù)目： | 2 |
| 電壓電源： | 模擬和數(shù)字 |
| 功率耗散（最大）： | 450mW |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 100-TQFP 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 100-TQFP-EP（14x14） |
| 包裝： | 托盤 |
| 輸出數(shù)目和類型： | 2 電流，單極；2 電流，雙極 |
| 采樣率（每秒）： | 800M |
| 產(chǎn)品目錄頁(yè)面： | 785 (CN2011-ZH PDF) |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)當(dāng)前第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)
AD9785/AD9787/AD9788
Rev. A | Page 28 of 64
The multichip synchronization register (MSCR) comprises four bytes located at Address 0x03.
Table 13. Multichip Synchronization Register (MSCR)
Address
Bit
Name
Description
0x03
[31:27]
Correlate Threshold
[4:0]
Sets the threshold for determining if the received synchronization data can be demodulated
accurately. A smaller threshold value makes the demodulator more noise immune; however,
the system becomes more susceptible to false locks (or demodulation errors).
[26]
SYNC_I enable
0: Default. The synchronization receive logic is disabled.
1: The synchronization receive logic is enabled.
[25]
SYNC_O enable
0: Default. The output synchronization pulse generation logic is disabled.
1: The output synchronization pulse generation logic is enabled.
[24]
Set low
This bit should always be set low.
[23:19]
SYNC_I Delay [4:0]
This value programs the value of the delay line of the SYNC_I signal. The delay line resolution
is 80 ps per step.
00000: nominal delay
00001: adds 80 ps delay to SYNC_I
00010: adds 160 ps delay to SYNC_I
…
11111: adds 2480 ps delay to SYNC_I
[18]
Sync error check mode
Specifies the synchronization pulse error check mode.
0: Manual error check
1: Automatic continuous error check
[17]
Set low
This bit should always be set low.
[16]
DATACLK input
0: Default. Slave mode is disabled.
1: Slave mode is enabled. Pin 37 functions as an input for the DATACLK signal, called DCI
(DATACLK input) in this mode. Depending on the state of Bit 1 in the DSCR register (Address
0x02), the sampling edge (where the data is latched into the AD9785/AD9787/AD9788) can
be programmed to be aligned with either the rising or falling edge of DCI. This mode can
only be used with 4× or 8× interpolation.
[15:11]
SYNC_O Delay [4:0]
This value programs the value of the delay line of the SYNC_O signal. The delay of SYNC_O is
relative to REFCLK. The delay line resolution is 80 ps per step.
00000: nominal delay
00001: adds 80 ps delay to SYNC_O
00010: adds 160 ps delay to SYNC_O
…
11111: adds 2480 ps delay to SYNC_O
[10]
Set high
This bit should always be set high.
[9]
SYNC_O polarity
0: Default. SYNC_O changes state on the rising edge of DACCLK.
1: SYNC_O is generated on the falling edge of DACCLK.
[8]
Sync loopback enable
0: Default. The AD9785/AD9787/AD9788 are not operating in internal loopback mode.
1: If the SYNC_O enable and Sync loopback enable bits are set, the AD9785/AD9787/AD9788
are operating in a mode in which the internal synchronization pulse of the device is used at
the multichip receiver logic and the SYNC_I+ and SYNC_I input pins are ignored. For proper
operation of the loopback synchronization mode, the synchronization driver enable and
sync enable bits must be set.
[7:4]
Clock State [3:0]
This value determines the state of the internal clock generation state machine upon
synchronization.
[3:0]
Sync Timing Margin
[3:0]
These bits are the synchronization window delay word. These bits are don’t care if the
synchronization driver enable bit is cleared.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MS27473E12F3PLC | CONN HSG PLUG 3POS STRGHT PINS |
| VE-J4Z-MZ-S | CONVERTER MOD DC/DC 2V 10W |
| MS27474E24A1S | CONN RCPT 128POS JAM NUT W/SCKT |
| MS27484T10B35B | CONN HSG PLUG 13POS STRGHT SCKT |
| VE-J4Y-MZ-S | CONVERTER MOD DC/DC 3.3V 16.5W |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD9785BSVZRL | 功能描述:IC DAC 12BIT 800MSPS 100TQFP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉(zhuǎn)換器 系列:TxDAC® 產(chǎn)品培訓(xùn)模塊:Data Converter Fundamentals DAC Architectures 標(biāo)準(zhǔn)包裝:750 系列:- 設(shè)置時(shí)間:7µs 位數(shù):16 數(shù)據(jù)接口:并聯(lián) 轉(zhuǎn)換器數(shù)目:1 電壓電源:雙 ± 功率耗散（最大）:100mW 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:28-LCC（J 形引線） 供應(yīng)商設(shè)備封裝:28-PLCC（11.51x11.51） 包裝:帶卷 (TR) 輸出數(shù)目和類型:1 電壓，單極；1 電壓，雙極 采樣率（每秒）:143k |
| AD9785-DPG2-EBZ | 功能描述:BOARD EVALUATION FOR AD9785 RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評(píng)估板 - 數(shù)模轉(zhuǎn)換器 (DAC) 系列:TxDAC® 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1 系列:- DAC 的數(shù)量:4 位數(shù):12 采樣率（每秒）:- 數(shù)據(jù)接口:串行，SPI? 設(shè)置時(shí)間:3µs DAC 型:電流/電壓 工作溫度:-40°C ~ 85°C 已供物品:板 已用 IC / 零件:MAX5581 |
| AD9785-EBZ | 制造商:Analog Devices 功能描述:Evaluation Board For AD9785 制造商:Analog Devices 功能描述:DUAL 12B, 1GSPS D-A CONVERTER - Bulk 制造商:Analog Devices 功能描述:Digital to Analog Eval. Board |
| AD9786 | 制造商:AD 制造商全稱:Analog Devices 功能描述:16-Bit, 200 MSPS/500 MSPS TxDAC+ with 2】/4】/8】 Interpolation and Signal Processing |
| AD9786BSV | 制造商:Analog Devices 功能描述:DAC 1-CH Interpolation Filter 16-bit 80-Pin TQFP EP 制造商:Analog Devices 功能描述:IC 16BIT DAC SMD 9786 TQFP80 |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。