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參數(shù)資料
| 型號： | AD9773AST |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | DAC |
| 英文描述： | 12-Bit, 160 MSPS 2】/4】/8】 Interpolating Dual TxDAC+ D/A Converter |
| 中文描述： | SERIAL INPUT LOADING, 12-BIT DAC, PQFP80 |
| 封裝： | 1.40 MM HEIGHT, PLASTIC, LQFP-80 |
| 文件頁數(shù)： | 11/19頁 |
| 文件大?。?/td> | 218K |
| 代理商： | AD9773AST |
AD9773
11
PRELIMINARY TECHNICAL DATA
Register Description
Address 00h
Bit 7
Logic 0 (default), causes the SDIO pin to act as an input during the data transfer (phase 2) of
the communications cycle. When set to a 1, SDIO can act as an input or output, depending on
bit 7 of the instruction byte.
Logic 0 (default). Determines the direction (LSB/MSB first) of the communications and data
transfer communications cycles. Refer to the section
MSB/LSB Transfers
on page 9 for a
detailed description.
Writing a one to this bit resets the registers to their default values and restarts the chip. The
RESET bit always reads back 0. Register address 0h bits are not cleared by this software reset.
However, a high level at the RESET pin forces all registers, including those in address 0h, to
their default state.
A logic 1 to this bit shuts down the DAC output currents.
Powerdown. Logic 1 shuts down all analog and digital functions.
1R/2R Mode. The default (0) places the AD9773 in 2 resistor mode. In this mode, the I
currents for the I and the Q DAC references are set separately by FSADJ1 and FSADJ2 on
pins 60 and 59. In this case, I
= 32*V
/FSADJ1 and I
= 32*V
/FSADJ2. With this
bit set to 1, the reference currents for both I and Q DACs are controlled by a single resistor on
pin 60. I
in one resistor mode for both the I and Q DACs = 16*V
/FSADJ1
PLL_LOCK indicator. When the PLL is enabled, reading this bit will give the status of the
PLL. A logic 1 indicates the PLL is locked. A logic 0 indicates an unlocked state.
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Address 01h
Bit 7,6
Filter interpolation rate according to the following table:
00
01
10
11
1
×
2
×
4
×
8
×
Bit 5,4
Modulation mode according to the following table:
00
01
10
11
none
fs/2
fs/4
fs/8
Address 01h
Bit 3
Logic 1 enables zero stuffing mode for interpolation filters
Default(1) enables the real mix mode. The I and Q data channels are individually modulated
by Fs/2,Fs/4 or Fs/8 after the interpolation filters. However, no complex modulation is done.
In the complex mix mode (logic 0), the digital modulators on the I and Q data channels are
coupled to create a digital complex modulator.When the AD9773 is applied in conjunction
with an external quadrature modulator, rejection can be achieved of either the higher or lower
frequency image around the 2nd IF frequency (i.e., the 2nd IF frequency is the LO of
the analog quadrature modulator external to the AD9773) according to the bit value of
register 01h, bit 1.
Logic 0(default) causes the complex modulation to be of the form e
-jwt
, resulting in the
rejection of the higher frequency image when the AD9773 is used with an external quadrature
modulator.A logic 1 causes the modulation to be of the form e
+jwt
, which causes rejection of
the lower frequency image
Bit 2
Bit 1
Address 02h
Bit 7
Logic 0 (default) causes data to be accepted on the inputs as 2
’
s complement binary. Logic 1
causes data to be accepted as straight binary.
Logic 0 (default) places the AD9773 in two port mode. I and Q data enters the AD9773 via
ports one and two, respectively. A logic 1 places the AD9773 in one port mode in which
interleaved I and Q data is applied to port one. See pin function descriptions for DATACLK/
PLL_LOCK, IQSEL and ONEPORTCLK for detailed information on how to use these
modes.
DATACLK driver strength. With the internal PLL disabled, and this bit set to logic 0, it is
recommended that DATACLK be buffered. When this bit is set to logic 1, DATACLK acts as
a stronger driver capable of driving small capacitive loads.
External dataclock. With the PLL disabled, pin 8 (DATACLK/PLL_LOCK) becomes a data
clock which must run at the same rate as the input data.If this bit is set to a 0 (default), pin 8 is
an output and theAD9773 creates this clock. If this bit is a logic 1, pin 8 is an input and an
external data clock must be applied and sychronized with the higher rate clock driving CLK+
and CLK-.
Bit 6
Bit 5
Bit 3
REV. PrA
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PDF描述 |
|---|---|
| AD9773EB | 12-Bit, 160 MSPS 2】/4】/8】 Interpolating Dual TxDAC+ D/A Converter |
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| AD9773BSV | 制造商:Analog Devices 功能描述:DAC 2-CH R-2R 12-bit 80-Pin TQFP EP 制造商:Rochester Electronics LLC 功能描述:12BIT 160 MSPS DUAL TXDAC+ D/A CONVERTER - Bulk 制造商:Analog Devices 功能描述:IC 12-BIT DAC |
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| AD9773BSVZ | 功能描述:IC DAC 12BIT DUAL 160MSPS 80TQFP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉(zhuǎn)換器 系列:TxDAC® 標準包裝:1 系列:- 設(shè)置時間:4.5µs 位數(shù):12 數(shù)據(jù)接口:串行，SPI? 轉(zhuǎn)換器數(shù)目:1 電壓電源:單電源 功率耗散（最大）:- 工作溫度:-40°C ~ 125°C 安裝類型:表面貼裝 封裝/外殼:8-SOIC（0.154"，3.90mm 寬） 供應(yīng)商設(shè)備封裝:8-SOICN 包裝:剪切帶 (CT) 輸出數(shù)目和類型:1 電壓，單極；1 電壓，雙極 采樣率（每秒）:* 其它名稱:MCP4921T-E/SNCTMCP4921T-E/SNRCTMCP4921T-E/SNRCT-ND |
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| AD9773EB | 制造商:AD 制造商全稱:Analog Devices 功能描述:12-Bit, 160 MSPS 2】/4】/8】 Interpolating Dual TxDAC+ D/A Converter |
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