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參數(shù)資料
| 型號： | AD97651 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | 12-Bit, 125 MSPS Dual TxDAC+ D/A Converter |
| 中文描述： | 12位，125 MSPS的TxDAC系列雙D / A轉(zhuǎn)換 |
| 文件頁數(shù)： | 9/28頁 |
| 文件大?。?/td> | 472K |
| 代理商： | AD97651 |
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REV. B
AD9765
–9–
FUNCTIONAL DESCRIPTION
Figure 20 shows a simplified block diagram of the AD9765.
The AD9765 consists of two DACs, each one with its own
independent digital control logic and full-scale output current
control. Each DAC contains a PMOS current source array
capable of providing up to 20 mA of full-scale current (I
OUTFS
).
The array is divided into 31 equal currents that make up the five
most significant bits (MSBs). The next four bits, or middle bits,
consist of 15 equal current sources whose value is 1/16th of an
MSB current source. The remaining LSB is a binary weighted
fraction of the middle bit current sources. Implementing the
middle and lower bits with current sources, instead of an R-2R
ladder, enhances the dynamic performance for multitone or low
amplitude signals and helps maintain the DAC’s high output
impedance (i.e., >100 k
).
All of these current sources are switched to one or the other of
the two output nodes (i.e., I
OUTA
or I
OUTB
) via PMOS differen-
tial current switches. The switches are based on a new architec-
ture that drastically improves distortion performance. This new
switch architecture reduces various timing errors and provides
matching complementary drive signals to the inputs of the dif-
ferential current switches.
The analog and digital sections of the AD9765 have separate
power supply inputs (i.e., AVDD and DVDD) that can operate
independently over a 3 V to 5.5 V range. The digital section,
which is capable of operating up to a 125 MSPS clock rate,
consists of edge-triggered latches and segment decoding logic
circuitry. The analog section includes the PMOS current sources,
the associated differential switches, a 1.20 V bandgap voltage
reference and two reference control amplifiers.
The full-scale output current of each DAC is regulated by sepa-
rate reference control amplifiers and can be set from 2 mA to
20 mA via an external resistor, R
SET
, connected to the Full
Scale Adjust (FSADJ) pin. The external resistor, in combination
with both the reference control amplifier and voltage reference
V
REFIO
, sets the reference current I
REF
, which is replicated to the
segmented current sources with the proper scaling factor. The
full-scale current, I
OUTFS
, is 32
×
I
REF
.
I
OUTA2
I
OUTB2
5V
I
OUTA1
I
OUTB1
SEGMENTED
SWITCHES FOR
DAC1
LSB
SWITCH
SEGMENTED
SWITCHES FOR
DAC2
LSB
SWITCH
DAC 2
LATCH
DAC 1
LATCH
CLK
DIVIDER
PMOS
CURRENT
SOURCE
ARRAY
PMOS
CURRENT
SOURCE
ARRAY
CLK1/IQCLK
CLK2/IQRESET
AVDD
FSADJ1
REFIO
FSADJ2
1.2V REF
CHANNEL 1 LATCH
CHANNEL 2 LATCH
MODE
DVDD
MULTIPLEXING LOGIC
5V
WRT2/
IQSEL
WRT1/
IQWRT
GAINCTRL
0.1 F
R
SET
2
2k
R
SET
1
2k
DCOM
SLEEP
ACOM
DB0
–
DB11
DB0
–
DB11
DIGITAL DATA INPUTS
AD9765
I
REF
1
I
REF
2
R
L
2B
50
R
L
2A
50
V
OUT
2B
V
OUT
2A
R
L
1B
50
R
L
1A
50
V
OUT
1B
V
OUT
1A
V
DIFF
= V
OUT
A
–
V
OUT
B
Figure 20. Simplified Block Diagram
REFERENCE OPERATION
The AD9765 contains an internal 1.20 V bandgap reference.
This can easily be overridden by an external reference with no
effect on performance. REFIO serves as either an
input
or
out-
put
, depending on whether the internal or an external reference
is used. To use the internal reference, simply decouple the
REFIO pin to ACOM with a 0.1
μ
F capacitor. The internal
reference voltage will be present at REFIO. If the voltage at
REFIO is to be used elsewhere in the circuit, an external buffer
amplifier with an input bias current of less than 100 nA should
be used. An example of the use of the internal reference is
shown in Figure 21.
+1.2V
REF
AVDD
GAINCTRL
CURRENT
SOURCE
ARRAY
REFIO
FSADJ
2k
0.1 F
ADDITIONAL
EXTERNAL
LOAD
OPTIONAL
EXTERNAL
REFERENCE
BUFFER
AD9765
REFERENCE
SECTION
I
REF
ACOM
Figure 21. Internal Reference Configuration
An external reference can be applied to REFIO as shown in
Figure 22. The external reference may provide either a fixed
reference voltage to enhance accuracy and drift performance or
a varying reference voltage for gain control. Note that the 0.1
μ
F
compensation capacitor is not required since the internal refer-
ence is overridden, and the relatively high input impedance of
REFIO minimizes any loading of the external reference.
+1.2V
REF
AVDD
GAINCTRL
CURRENT
SOURCE
ARRAY
REFIO
FSADJ
2k
AD9765
REFERENCE
SECTION
I
REF
ACOM
AVDD
EXTERNAL
REFERENCE
Figure 22. External Reference Configuration
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| AD9765AST | 功能描述:數(shù)模轉(zhuǎn)換器- DAC 12-Bit 125 MSPS Dual TxDAC+ RoHS:否 制造商:Texas Instruments 轉(zhuǎn)換器數(shù)量:1 DAC 輸出端數(shù)量:1 轉(zhuǎn)換速率:2 MSPs 分辨率:16 bit 接口類型:QSPI, SPI, Serial (3-Wire, Microwire) 穩(wěn)定時(shí)間:1 us 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:SOIC-14 封裝:Tube |
| AD9765ASTRL | 制造商:Analog Devices 功能描述:DAC 2-CH Segment 12-bit 48-Pin LQFP T/R 制造商:Analog Devices 功能描述:DAC DUAL CURRENT STEERING 12-BIT 48LQFP - Tape and Reel 制造商:Rochester Electronics LLC 功能描述:12-BIT, 125 MSPS DUAL TXDAC+ - Tape and Reel 制造商:Analog Devices Inc. 功能描述:Digital to Analog Converters - DAC 12-Bit 125 MSPS Dual TxDAC+ 制造商:Analog Devices Inc. 功能描述:Digital to Analog Converters - DAC 12-Bit 125 MSPS Dual 制造商:Analog Devices 功能描述:CONVERTER - DAC |
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| AD9765ASTZKL1 | 制造商:Rochester Electronics LLC 功能描述: 制造商:Analog Devices 功能描述: |
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