參數(shù)資料
型號(hào)： AD97651
廠商： Analog Devices, Inc.
英文描述： 12-Bit, 125 MSPS Dual TxDAC+ D/A Converter
中文描述： 12位，125 MSPS的TxDAC系列雙D / A轉(zhuǎn)換
文件頁(yè)數(shù)： 16/28頁(yè)
文件大?。?/td> 472K
代理商： AD97651
REV. B
AD9765
–16–
FREQUENCY
–
MHz
P
–
90
70
0.2
85
80
75
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
1.1
Figure 38. Power Supply Rejection Ratio of AD9765
Note that the units in Figure 38 are given in units of (amps out/
volts in). Noise on the analog power supply has the effect of
modulating the internal current sources, and therefore the out-
put current. The voltage noise on AVDD, therefore, will be
added in a nonlinear manner to the desired I
OUT
. PSRR is very
code dependent thus producing mixing effects which can modu-
late low frequency power supply noise to higher frequencies.
Worst case PSRR for either one of the differential DAC outputs
will occur when the full-scale current is directed towards that
output. As a result, the PSRR measurement in Figure 38 repre-
sents a worst case condition in which the digital inputs remain
static and the full-scale output current of 20 mA is directed to
the DAC output being measured.
An example serves to illustrate the effect of supply noise on the
analog supply. Suppose a switching regulator with a switching
frequency of 250 kHz produces 10 mV of noise and, for simplic-
ity sake (i.e., ignore harmonics), all of this noise is concentrated
at 250 kHz. To calculate how much of this undesired noise will
appear as current noise superimposed on the DAC’s full-scale
current, I
OUTFS
, one must determine the PSRR in dB using
Figure 38 at 250 kHz. To calculate the PSRR for a given R
LOAD
,
such that the units of PSRR are converted from A/V to V/V,
adjust the curve in Figure 38 by the scaling factor 20
×
Log
(R
LOAD
). For instance, if R
LOAD
is 50
, the PSRR is reduced
by 34 dB (i.e., PSRR of the DAC at 250 kHz, which is 85 dB in
Figure 38, becomes 51 dB V
OUT
/V
IN
).
Proper grounding and decoupling should be a primary objective
in any high speed, high resolution system. The AD9765 features
separate analog and digital supply and ground pins to optimize
the management of analog and digital ground currents in a
system. In general, AVDD, the analog supply, should be de-
coupled to ACOM, the analog common, as close to the chip as
physically possible. Similarly, DVDD, the digital supply, should
be decoupled to DCOM as close to the chip as physically possible.
For those applications that require a single +5 V or +3 V supply
for both the analog and digital supplies, a clean analog supply
may be generated using the circuit shown in Figure 39. The
circuit consists of a differential LC filter with separate power
supply and return lines. Lower noise can be attained by using
low ESR type electrolytic and tantalum capacitors.
100 F
10 F
–
22 F
0.1 F
TTL/CMOS
LOGIC
CIRCUITS
+5V
POWER SUPPLY
FERRITE
BEADS
AVDD
ACOM
ELECTROLYTIC
TANTALUM
CERAMIC
Figure 39. Differential LC Filter for Single +5 V and +3 V
Applications
APPLICATIONS
VDSL Applications Using the AD9765
Very High Frequency Digital Subscriber Line (VDSL) technol-
ogy is growing rapidly in applications requiring data transfer
over relatively short distances. By using QAM modulation and
transmitting the data in Discrete Multiple Tones (DMT), high
data rates can be achieved.
As with other multitone applications, each VDSL tone is ca-
pable of transmitting a given number of bits, depending on the
signal-to-noise ratio (SNR) in a narrow band around that tone.
For a typical VDSL application, the tones are evenly spaced
over the range of several kHz to 10 MHz. At the high frequency
end of this range, performance is generally limited by cable
characteristics and environmental factors, such as external inter-
ferers. Performance at the lower frequencies is much more de-
pendent on the performance of the components in the signal
chain. In addition to in-band noise, intermodulation from other
tones can also potentially interfere with the data recovery for a
given tone. The two graphs in Figure 40 represent a 500-tone
missing bin test vector, with frequencies evenly spaced from
400 Hz to 10 MHz. This test is very commonly done to deter-
mine if distortion will limit the number of bits that can be trans-
mitted in a tone. The test vector has a series of missing tones
around 750 kHz, which is represented in Figure 40a, and a
series of missing tones around 5 MHz, which is represented in
Figure 40b. In both cases, the spurious free dynamic range
(SFDR) between the transmitted tones and the empty bins is
greater than 60 dB.
FREQUENCY
–
MHz
d
0.665
–
90
–
80
–
70
–
60
–
50
–
40
–
30
–
20
–
100
–
120
–
110
0.685 0.705 0.725 0.745 0.765 0.785 0.805
0.825
Figure 40a. Notch in Missing Bin at 750 kHz Is Down
>60 dB (Peak Amplitude = 0 dBm)
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