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參數(shù)資料
| 型號： | AD9763-EB |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | 10-Bit, 125 MSPS Dual TxDAC+ D/A Converter |
| 中文描述： | 10位，125 MSPS的TxDAC系列雙D / A轉換 |
| 文件頁數(shù)： | 13/28頁 |
| 文件大?。?/td> | 460K |
| 代理商： | AD9763-EB |
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REV. B
AD9763
–
13
–
Note that the clock input could also be driven via a sine wave,
which is centered around the digital threshold (i.e., DVDD/2)
and meets the min/max logic threshold. This will typically result
in a slight degradation in the phase noise, which becomes more
noticeable at higher sampling rates and output frequencies.
Also, at higher sampling rates, the 20% tolerance of the digital
logic threshold should be considered since it will affect the effec-
tive clock duty cycle and, subsequently, cut into the required
data setup and hold times.
DVDD
DIGITAL
INPUT
Figure 28. Equivalent Digital Input
INPUT CLOCK AND DATA TIMING RELATIONSHIP
SNR in a DAC is dependent on the relationship between the
position of the clock edges and the point in time at which the
input data changes. The AD9763 is rising edge triggered, and so
exhibits SNR sensitivity when the data transition is close to this
edge. In general, the goal when applying the AD9763 is to make
the data transition close to the falling clock edge. This becomes
more important as the sample rate increases. Figure 29 shows
the relationship of SNR to clock placement with different
sample rates. Note that at the lower sample rates, much more
tolerance is allowed in clock placement, while much more care
must be taken at higher rates.
TIME OF DATA CHANGE RELATIVE TO
RISING CLOCK EDGE
–
ns
S
–
0
–
4
–
2
0
2
3
–
3
–
1
4
1
10
20
30
40
50
60
70
Figure 29. SNR vs. Clock Placement @ f
OUT
= 20 MHz and
f
CLK
= 125 MSPS
SLEEP MODE OPERATION
The AD9763 has a power-down function that turns off the
output current and reduces the supply current to less than
8.5 mA over the specified supply range of 3.0 V to 5.5 V and
temperature range. This mode can be activated by applying a
Logic Level “1” to the SLEEP pin. The SLEEP pin logic thresh-
old is equal to 0.5
×
AVDD. This digital input also contains an
active pull-down circuit that ensures the AD9763 remains enabled
if this input is left disconnected. The AD9763 takes less than
50 ns to power down and approximately 5
μ
s to power back up.
POWER DISSIPATION
The power dissipation, P
D
, of the AD9763 is dependent on
several factors that include: (1) The power supply voltages
(AVDD and DVDD), (2) the full-scale current output I
OUTFS
,
(3) the update rate f
CLOCK
, (4) and the reconstructed digital
input waveform. The power dissipation is directly proportional
to the analog supply current, I
AVDD
, and the digital supply current,
I
DVDD
. I
AVDD
is directly proportional to I
OUTFS
as shown in
Figure 30 and is insensitive to f
CLOCK
.
I
OUTFS
0
5
10
10
I
A
20
30
40
50
60
70
80
15
20
25
Figure 30. I
AVDD
vs. I
OUTFS
Conversely, I
DVDD
is dependent on both the digital input wave-
form, f
CLOCK
, and digital supply DVDD. Figures 31 and 32
show I
DVDD
as a function of full-scale sine wave output ratios
(f
OUT
/f
CLOCK
) for various update rates with DVDD = 5 V and
DVDD = 3 V, respectively. Note how I
DVDD
is reduced by more
than a factor of 2 when DVDD is reduced from 5 V to 3 V.
RATIO
–
f
OUT
/f
CLK
0
0.10
0
I
D
–
5
10
15
20
25
30
35
0.20
0.30
0.40
0.50
125MSPS
100MSPS
65MSPS
25MSPS
5MSPS
Figure 31. I
DVDD
vs. Ratio @ DVDD = 5 V
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PDF描述 |
|---|---|
| AD9763AST | 10-Bit, 125 MSPS Dual TxDAC+ D/A Converter |
| AD9764 | 14-Bit, 125 MSPS TxDAC D/A Converter |
| AD9764-EB | 14-Bit, 125 MSPS TxDAC D/A Converter |
| AD9764AR | 14-Bit, 125 MSPS TxDAC D/A Converter |
| AD9764ARU | 14-Bit, 125 MSPS TxDAC D/A Converter |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| AD9763-EBZ | 功能描述:BOARD EVAL FOR AD9763 RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評估板 - 數(shù)模轉換器 (DAC) 系列:TxDAC+® 產品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:1 系列:- DAC 的數(shù)量:4 位數(shù):12 采樣率（每秒）:- 數(shù)據(jù)接口:串行，SPI? 設置時間:3µs DAC 型:電流/電壓 工作溫度:-40°C ~ 85°C 已供物品:板 已用 IC / 零件:MAX5581 |
| AD9764 | 制造商:Analog Devices 功能描述: |
| AD9764AR | 功能描述:IC DAC 14BIT 125MSPS 28-SOIC RoHS:否 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉換器 系列:TxDAC® 產品培訓模塊:Data Converter Fundamentals DAC Architectures 標準包裝:750 系列:- 設置時間:7µs 位數(shù):16 數(shù)據(jù)接口:并聯(lián) 轉換器數(shù)目:1 電壓電源:雙 ± 功率耗散（最大）:100mW 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:28-LCC（J 形引線） 供應商設備封裝:28-PLCC（11.51x11.51） 包裝:帶卷 (TR) 輸出數(shù)目和類型:1 電壓，單極；1 電壓，雙極 采樣率（每秒）:143k |
| AD9764ARRL | 功能描述:IC DAC 14BIT 125MSPS 28-SOIC RoHS:否 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉換器 系列:TxDAC® 標準包裝:47 系列:- 設置時間:2µs 位數(shù):14 數(shù)據(jù)接口:并聯(lián) 轉換器數(shù)目:1 電壓電源:單電源 功率耗散（最大）:55µW 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:28-SSOP（0.209"，5.30mm 寬） 供應商設備封裝:28-SSOP 包裝:管件 輸出數(shù)目和類型:1 電流，單極；1 電流，雙極 采樣率（每秒）:* |
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