參數(shù)資料
型號(hào)： AD9761
廠商： Analog Devices, Inc.
英文描述： Dual 10-Bit TxDAC with 23 Interpolation Filters(內(nèi)插濾波器的雙10位D/A轉(zhuǎn)換器)
中文描述： 雙10與23位插值濾波器TxDAC系列（內(nèi)插濾波器的雙10位的D / A轉(zhuǎn)換器）
文件頁(yè)數(shù)： 14/24頁(yè)
文件大?。?/td> 294K
代理商： AD9761
AD9761
–14–
REV. 0
some address decode logic. T he I and Q filter registers of both
devices are simultaneously loaded on the rising edge of CLOCK
upon latching the Q sample pertaining to device B. Note that
WRIT E A or WRIT E B can also be tied to CLOCK to accom-
plish this.
T he digital inputs are CMOS compatible with logic thresholds,
V
T HRESHOLD
set to approximately half the digital positive supply
(DVDD) or
V
THRESHOLD
= DVDD
/2 (
±
20%).
T he internal digital circuitry of the AD9761 is capable of oper-
ating over a digital supply range of 2.7 V to 5.5 V. As a result,
the digital inputs can also accommodate T T L levels when DVDD
is set to accommodate the maximum high level voltage, V
OH(MAX )
,
of the T T L drivers. A DVDD of 3 V to 3.3 V will typically
ensure proper compatibility of most T T L logic families. Figure
31 shows the equivalent digital input circuit for the data, sleep
and clock inputs.
RESET
DATA
SELECT
CLOCK/WRITE
I
0
Q
0
I
1
Q
1
Figure 30a.
RESET
DATA
SELECT
WRITE "A"
WRITE "B"
CLOCK
I-A
I-B
Q-A
Q-B
Figure 30b.
DVDD
DIGITAL
INPUT
Figure 31. Equivalent Digital Input
Since the AD9761 is capable of being updated up to 40 MSPS,
the quality of the clock and data input signals are important in
achieving the optimum performance. T he drivers of the digital
data interface circuitry should be specified to meet the minimum
setup and hold-times of the AD9761 as well as its required min/
max input logic level thresholds. T he external clock driver cir-
cuitry should provide the AD9761 with a low jitter clock input
meeting the min/max logic levels while providing fast edges. Fast
clock edges will help minimize any jitter that can manifest itself
as phase noise on a reconstructed waveform.
Digital signal paths should be kept short, and run lengths
matched to avoid propagation delay mismatch. T he insertion of
a low value resistor network (i.e., 20
to 100
) between the
AD9761 digital inputs and driver outputs may be helpful in
reducing any overshooting and ringing at the digital inputs,
which contributes to data feedthrough. Operating the AD9761
with reduced logic swings and a corresponding digital supply
(DVDD) will also reduce data feedthrough.
RE SE T /SLE E P MODE OPE RAT ION
T he RESET /SLEEP input can be used either to power-down the
AD9761 or reset its internal digital interface logic. If the RESET /
SLEEP input is asserted for greater than one clock cycle but
under four clock cycles by applying a logic level “1,” the internal
state machine will be reset. If the RESET /SLEEP input is as-
serted for four clock cycles or longer, the power-down function
of the AD9761 will be initiated. T he power-down function turns
off the output current and reduces the supply current to less than
9 mA over the specified supply range of 2.7 V to 5.5 V and tem-
perature range.
T he power-up and power-down characteristics of the AD9761 is
dependent upon the value of the compensation capacitor connected
to COMP1 and COMP3. With a nominal value of 0.1
μ
F, the
AD9761 takes less than 5
μ
s to power down and approximately
3.25 ms to power back up.
POWE R DISSIPAT ION
T he power dissipation of the AD9761 is dependent on several
factors which include: (1) AVDD and DVDD, the power supply
voltages; (2) I
OUT FS
, the full-scale current output; (3) f
CLOCK
, the
update rate; (4) and the reconstructed digital input waveform.
T he power dissipation is directly proportional to the analog
supply current, I
AVDD
, and the digital supply current, I
DVDD
.
I
AVDD
is directly proportional to I
OUT FS
as shown in Figure 32
and is insensitive to f
CLOCK
.
相關(guān)PDF資料
PDF描述
AD9762 Analog Devices: Data Converters: DAC 12-Bit, 10 ns to 100 ns Converters Selection Table
AD9762-EB 12-Bit, 125 MSPS TxDAC D/A Converter
AD9762AR 12-Bit, 125 MSPS TxDAC D/A Converter
AD9762ARU 12-Bit, 125 MSPS TxDAC D/A Converter
AD9765 Analog Devices: Data Converters: DAC 12-Bit, 10 ns to 100 ns Converters Selection Table
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